MMA8452QR1 Freescale Semiconductor, MMA8452QR1 Datasheet - Page 45

• Manufacturer Part Number: MMA8452QR1
• Description: Board Mount Accelerometers LOW G 3-AXIS 12BT EX VLT
• Manufacturer: Freescale Semiconductor

Specifications of MMA8452QR1

• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 4 g, 8 g
• Digital Output - Number Of Bits: 8 bit, 12 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.95 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Digital Output - Bus Interface: I2C
• Shutdown: Yes
• Sensitivity: 256 count/g, 512 count/g, 1024 count/g
• Package / Case: QFN-16
• Output Type: Digital
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Acceleration Range: ± 2g, ± 4g, ± 8g
• No. Of Axes: 3
• Ic Interface Type: I2C
• Sensor Case Style: QFN
• No. Of Pins: 16
• Supply Voltage Range: 1.95V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 66. MMA8452Q Register Map
Sensors
Freescale Semiconductor
Reg
0C
0D
1D
2C
2D
00
01
02
03
04
05
06
0B
0E
0F
10
11
12
13
14
15
16
17
18
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2E
2F
30
31
HP_FILTER_CUTOFF
TRANSIENT_COUNT
TRANSIENT_CFG
TRANSIENT_SRC
TRANSIENT_THS
XYZ_DATA_CFG
PL_BF_ZCOMP
FF_MT_COUNT
P_L_THS_REG
INT_SOURCE
PULSE_THSX
PULSE_THSY
PULSE_THSZ
PULSE_TMLT
PULSE_WIND
ASLP_COUNT
PULSE_LTCY
OUT_X_MSB
OUT_Y_MSB
OUT_Z_MSB
PULSE_CFG
PULSE_SRC
OUT_X_LSB
OUT_Y_LSB
OUT_Z_LSB
PL_STATUS
FF_MT_CFG
FF_MT_SRC
FF_MT_THS
CTRL_REG1
CTRL_REG2
CTRL_REG3
CTRL_REG4
CTRL_REG5
WHO_AM_I
PL_COUNT
SYSMOD
STATUS
PL_CFG
OFF_X
OFF_Y
OFF_Z
Name
Freefall/Motion Threshold
Freefall/Motion Debounce
Transient Threshold R/W
(Interrupt Configuration)
Pulse X Threshold R/W
Pulse Y Threshold R/W
Pulse Z Threshold R/W
PL Back/Front Z Comp
Freefall/Motion Source
(WAKE Interrupts from
PL THRESHOLD R/W
(Interrupt Enable Map)
PL Configuration R/W
Freefall/Motion Config
Pulse First Timer R/W
HP Filter Setting R/W
PL DEBOUNCE R/W
Transient Config R/W
Auto-SLEEP Counter
Transient Debounce
Transient Source R
Pulse Latency R/W
Pulse 2nd Window
Control Reg1 R/W
Control Reg2 R/W
Pulse Config R/W
Interrupt Status R
X 8-bit offset R/W
Y 8-bit offset R/W
Z 8-bit offset R/W
Data Config R/W
System Mode R
Pulse Source R
14 bit X Data R
14 bit X Data R
14 bit Y Data R
14 bit Y Data R
14 bit Z Data R
14 bit Z Data R
Data Status R
ID Register R
Control Reg3
SLEEP) R/W
Control Reg4
Control Reg5
PL Status R
Definition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
INT_CFG_ASLP
INT_EN_ASLP
ASLP_RATE1
P_L_THS[4]
SRC_ASLP
DBNCE[7]
DBCNTM
DBCNTM
DBCNTM
ZYXOW
BKFR[1]
NEWLP
WIND7
TMLT7
LTCY7
Bit 7
DPA
XD9
XD1
YD9
YD1
ZD9
ZD1
ELE
EA
D7
D7
EA
D7
ST
D7
D7
D7
0
0
0
0
0
0
0
0
0
0
WAKE_TRANS
ASLP_RATE0
P_L_THS[3]
DBNCE[6]
BKFR[0]
PL_EN
THSX6
THSY6
THSZ6
TMLT6
LTCY6
WIND6
THS6
THS6
ZOW
Bit 6
OAE
XD8
XD0
YD8
YD0
ZD8
ZD0
ELE
RST
AxZ
LO
EA
D6
D6
D6
D6
D6
D6
0
0
0
0
0
0
0
0
0
INT_CFG_TRANS
Pulse_HPF_BYP
WAKE_LNDPRT
INT_EN_TRANS
SRC_TRANS
P_L_THS[2]
DBNCE[5]
ZTRANSE
ZDPEFE
THSX5
THSY5
WIND5
THSZ5
TMLT5
LTCY5
ZEFE
THS5
THS5
YOW
Bit 5
DR2
XD7
YD7
ZD7
ZHE
AxY
D5
D5
D5
D5
D5
D5
0
0
0
0
1
0
0
0
0
0
0
INT_CFG_LNDPRT
INT_EN_LNDPRT
Pulse_LPF_EN
WAKE_PULSE
SRC_LNDPRT
Z_Trans_Pol
P_L_THS[1]
HPF_OUT
DBNCE[4]
SMODS1
ZSPEFE
THSX4
THSY4
THSZ4
TMLT4
LTCY4
WIND4
YEFE
XOW
THS4
THS4
Bit 4
XD6
YD6
ZD6
ZHP
ELE
DR1
AxX
D4
D4
D4
D4
D4
D4
0
0
0
0
0
0
0
0
INT_CFG_PULSE
INT_EN_PULSE
WAKE_FF_MT
SRC_PULSE
P_L_THS[0]
DBNCE[3]
YTRANSE
SMODS0
YDPEFE
ZYXDR
ZTEFE
THSX3
THSY3
THSZ3
TMLT3
LTCY3
WIND3
XEFE
THS3
THS3
Bit 3
YHE
DPE
XD5
YD5
ZD5
DR0
D3
D3
D3
D3
D3
D3
0
0
0
0
1
0
0
0
0
0
INT_CFG_FF_MT
INT_EN_FF_MT
SRC_FF_MT
Y_Trans_Pol
DBNCE[2]
ZLOCK[2]
YSPEFE
LAPO[1]
LNOISE
HYS[2]
YTEFE
THSX2
THSY2
THSZ2
TMLT2
LTCY2
WIND2
Pol_Z
THS2
THS2
SLPE
Bit 2
ZDR
XD4
YD4
ZD4
YHP
D2
D2
D2
D2
D2
D2
0
0
0
0
0
0
0
0
0
0
SYSMOD1
XTRANSE
DBNCE[1]
ZLOCK[1]
XDPEFE
F_READ
LAPO[0]
MODS1
XTEFE
THSX1
THSY1
WIND1
HYS[1]
THSZ1
TMLT1
LTCY1
THS1
THS1
Pol_Y
SEL1
IPOL
Bit 1
YDR
XHE
XD3
YD3
ZD3
FS1
D1
D1
D1
D1
D1
D1
0
0
0
0
1
0
0
0
0
MMA8452Q
INT_CFG_DRDY
INT_EN_DRDY
X_Trans_Pol
SRC_DRDY
SYSMOD0
DBNCE[0]
HPF_BYP
ZLOCK[0]
XSPEFE
ACTIVE
BAFRO
MODS0
PP_OD
HYS[0]
THSX0
THSY0
THSZ0
TMLT0
LTCY0
WIND0
Pol_X
SEL0
THS0
THS0
Bit 0
XDR
XD2
YD2
ZD2
XHP
FS0
D0
D0
D0
D0
D0
D0
0
0
0
0
0
0
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