LIS3DH STMicroelectronics, LIS3DH Datasheet
LIS3DH
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LIS3DH Summary of contents
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... Thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS3DH has an integrated 32-level first in, first out (FIFO) buffer allowing the user to store data for host processor intervention reduction. The LIS3DH is available in small thin plastic land grid ...
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... Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.1 2/42 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Normal mode, low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 17530 Rev 1 LIS3DH ...
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... LIS3DH 5.1.2 5.1.3 5.1.4 5.1.5 6 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1.1 6.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.1 6.2.2 6.2.3 7 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 STATUS_AUX (07h 8.2 OUT_1_L (08h), OUT_1_H (09h 8.3 OUT_2_L (0Ah), OUT_2_H (0Bh 8.4 OUT_3_L (0Ch), OUT_3_H (0Dh ...
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... FIFO_SRC_REG (2Fh 8.21 INT1_CFG (30h 8.22 INT1_SRC (31h 8.23 INT1_THS (32h 8.24 INT1_DURATION (33h 8.25 CLICK_CFG (38h 8.26 CLICK_SRC (39h 8.27 CLICK_THS (3Ah 8.28 TIME_LIMIT (3Bh 8.29 TIME_LATENCY (3Ch 8.30 TIME WINDOW(3Dh Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4/42 Doc ID 17530 Rev 1 LIS3DH ...
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... Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. I2C Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. LIS3DH electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8. Multiple bytes SPI read protocol (2 bytes example Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10 ...
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... REFERENCE register Table 39. REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 40. STATUS register Table 41. STATUS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 42. REFERENCE register Table 43. REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 44. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 45. FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 46. INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 47. INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 48. Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6/42 Doc ID 17530 Rev 1 LIS3DH ...
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... LIS3DH Table 49. INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 50. INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 51. INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 52. INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 53. INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 54. INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 55. CLICK_CFG register Table 56. CLICK_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 57. CLICK_SRC register Table 58. CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 59. CLICK_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 60. CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 61. TIME_LIMIT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 62. ...
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... TEMPERATURE SENSOR TRIMMING REFERENCE CLOCK CIRCUITS Z 1 Doc ID 17530 Rev 1 CS SCL/SPC I2C CONTROL LOGIC SDA/SDO/SDI SPI SDO/SA0 CONTROL LOGIC 96 Level & FIFO INTERRUPT GEN. Pin 1 indicator 13 1 ADC3 Vdd_IO GND NC INT1 NC RES SCL/SPC 9 INT2 5 GND (BOTTOM VIEW) LIS3DH INT 1 INT 2 ...
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... LIS3DH Table 2. Pin description Pin Name Vdd_IO Power supply for I/O pins NC Not connected NC Not connected 2 SCL I C serial clock (SCL) SPC SPI serial port clock (SPC) GND 0V supply 2 SDA I C serial data (SDA) SDI SPI serial data input (SDI) SDO ...
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... FS bit set to 00 Max delta from 25 °C FS bit set to 00, Normal Mode (Table 9), ODR = 100Hz FS bit set axis FS bit set axis FS bit set axis . 1LSb=1mg, ±2 g Full-scale. (CTRL_REG4 ST bit=0) Doc ID 17530 Rev 1 LIS3DH (1) Min. Typ. Max. Unit ±2.0 ±4.0 ±8.0 ±16.0 1 mg/digit 2 mg/digit ...
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... LIS3DH 2.2 Temperature sensor characteristics Vdd =2.5 V, T=25 °C unless otherwise noted Table 4. Temperature sensor characteristics Symbol Parameter Temperature sensor output change vs TSDr temperature TODR Temperature refresh rate Top Operating temperature range 1. Typical specifications are not guaranteed. 2. 8-bit resolution. 2.3 Electrical characteristics Vdd = 2 ° ...
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... Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port. 3 When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors. 12/42 Parameter t c(SPC) t h(SI) MSB v(SO) h(SO) MSB OUT Doc ID 17530 Rev 1 LIS3DH (1) Value Unit Min Max 100 ns 10 MHz ...
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... LIS3DH 2 2.4 Inter IC control interface Subject to general operating conditions for Vdd and top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time ...
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... This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part. This is an ESD sensitive device, improper handling can cause permanent damages to the part. 14/42 Ratings Doc ID 17530 Rev 1 LIS3DH Maximum value Unit -0.3 to 4.8 V -0.3 to 4.8 V -0.3 to Vdd_IO +0.3 V 3000 for 0 ...
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... Functionality 3.2.1 Normal mode, low power mode LIS3DH provides two different operating modes respectively reported as normal mode and low power mode. While normal mode guarantees high resolution, low power mode reduces further the current consumption. The table below reported summarizes how to select the operating mode. ...
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... The LIS3DH may also be configured to generate an inertial Wake-Up and Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both Free- Fall and Wake-Up can be available simultaneously on two different pins. ...
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... This allows to use the device without further calibration. 3.6 FIFO The LIS3DH contains a 10 bit, 32-level FIFO. Buffered output allows 4 operation modes: FIFO, stream, trigger and FIFO ByPass. Where FIFO bypass mode is activated FIFO is not operating and remains empty. In FIFO mode, data from acceleration detection and z- axes measurements are stored in FIFO ...
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... Application hints 4 Application hints Figure 5. LIS3DH electrical connection Vdd Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF aluminum) should be placed as near as possible to the pin 14 of the device (common design practice) ...
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... FIFO LIS3DH embeds a 32-slot of 10bit data FIFO for each of the three output channels and Z. This allows a consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wakeup only when needed and burst the significant data out from the FIFO ...
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... Digital interfaces 6 Digital interfaces The registers embedded inside the LIS3DH may be accessed through both the I serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I line must be tied high (i.e. connected to Vdd_IO). ...
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... The I C embedded inside the LIS3DH behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address (SUB) is transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is ‘ ...
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... Master Acknowledge. 6.2 SPI bus interface The LIS3DH SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 6. Read and write protocol ...
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... LIS3DH SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the read register and write register commands are completed in 16 clock pulses or in multiple case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC ...
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... DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 AD5 AD4 AD3 AD2 AD1 AD0 Doc ID 17530 Rev 1 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 LIS3DH ...
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... LIS3DH 6.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) in CTRL_REG4. Figure 11. SPI read protocol in 3-wires mode CS SPC SDI/O The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. ...
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... Doc ID 17530 Rev 1 LIS3DH Default Comment Reserved output output output output output output Reserved output output output output output output ...
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... LIS3DH Table 17. Register address map Name INT1_SOURCE INT1_THS INT1_DURATION Reserved CLICK_CFG CLICK_SRC CLICK_THS TIME_LIMIT TIME_LATENCY TIME_WINDOW Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values ...
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... The value is expressed in two’s complement. 8.3 OUT_2_L (0Ah), OUT_2_H (0Bh) 2-axis acceleration data. The value is expressed in two’s complement. 8.4 OUT_3_L (0Ch), OUT_3_H (0Dh) 3-axis acceleration data. The value is expressed in two’s complement. 28/42 2OR 1OR 321DA Doc ID 17530 Rev 1 LIS3DH 3DA 2DA 1DA ...
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... LIS3DH 8.5 INT_COUNTER (0Eh) Table 20. INT_COUNTER register IC7 IC6 8.6 WHO_AM_I (0Fh) Table 21. WHO_AM_I register 0 0 Device identification register. 8.7 TEMP_CFG_REG (1Fh) Table 22. TEMP_CFG_REG register ADC_PD TEMP_EN Table 23. TEMP_CFG_REG description ADC enable. Default value: 0 ADC_PD (0: ADC disabled; 1: ADC enabled) Temperature sensor (T) enable. Default value: 0 TEMP_EN (0: T disabled ...
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... Normal / low power mode (100 Hz Normal / low power mode (200 Hz Normal / low power mode (400 Hz Low power mode (1.6 KHz Normal (1.25 kHz) / low power mode (5 KHz) HPCF2 HPCF1 FDS Doc ID 17530 Rev 1 LIS3DH Power mode selection HPCLICK HPIS2 HPIS1 ...
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... LIS3DH Table 29. High pass filter mode configuration HPM1 HPM0 8.10 CTRL_REG3 (22h) Table 30. CTRL_REG3 register I1_CLICK I1_AOI1 Table 31. CTRL_REG3 description I1_CLICK I1_AOI1 I1_AOI2 I1_DRDY1 I1_DRDY2 I1_WTM I1_OVERRUN 8.11 CTRL_REG4 (23h) Table 32. CTRL_REG4 register BDU BLE Table 33. CTRL_REG4 description BDU BLE FS1-FS0 ...
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... Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by reading INT1_SRC itself. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) 4D enable: 4D detection is enabled on INT1 when 6D bit on INT1_CFG is set BOOT_I1 0 Ref5 Ref4 Ref3 Doc ID 17530 Rev 1 Table 34) Self test mode H_LACTIVE - Ref2 Ref1 Ref0 LIS3DH ...
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... LIS3DH Table 39. REFERENCE register description Ref 7-Ref0 8.15 STATUS_REG (27h) Table 40. STATUS register ZYXOR ZOR Table 41. STATUS register description ZYXOR X, Y and Z axis data overrun. Default value: 0 (0: no overrun has occurred new set of data has overwritten the previous ones) ZOR Z axis data overrun. Default value: 0 (0: no overrun has occurred ...
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... Bypass mode 1 FIFO mode 0 Stream mode 1 Trigger mode EMPTY FSS4 ZHIE/ ZLIE/ YHIE/ ZDOWNE YUPE Doc ID 17530 Rev 1 FTH3 FTH2 FTH1 Table 44 ) Self test mode FSS3 FSS2 FSS1 YLIE/ XHIE/ YDOWNE XUPE Table 48, "Inter- Table 48, "Interrupt LIS3DH FTH0 FSS0 XLIE/ XDOWNE ...
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... LIS3DH Table 47. INT1_CFG description ZLIE/ Enable interrupt generation on Z low event or on Direction recognition. Default ZDOWNE value: 0 (0: disable interrupt request;1: enable interrupt request) YHIE/ Enable interrupt generation on Y high event or on Direction recognition. Default YUPE value: 0 (0: disable interrupt request; 1: enable interrupt request.) YLIE/ Enable interrupt generation on Y low event or on Direction recognition ...
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... bits set the minimum duration of the Interrupt 1 event to be recognized. Duration steps and maximum values depend on the ODR chosen. 8.25 CLICK_CFG (38h) Table 55. CLICK_CFG register -- -- 36/42 THS5 THS4 Interrupt 1 threshold. Default value: 000 0000 D5 D4 Duration value. Default value: 000 0000 Doc ID 17530 Rev 1 THS3 THS2 THS1 LIS3DH THS0 D0 XS ...
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... LIS3DH Table 56. CLICK_CFG description 8.26 CLICK_SRC (39h) Table 57. CLICK_SRC register IA Table 58. CLICK_SRC description - - IA Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) DCLICK Double CLICK-CLICK enable. Default value: 0 (0:double CLICK-CLICK detection dis- able, 1: double CLICK-CLICK detection enable) SCLICK Single CLICK-CLICK enable ...
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... TLI4 TLI3 CLICK-CLICK Time Limit. Default value: 000 0000 TLA5 TLA4 TLA3 CLICK-CLICK time latency. Default value: 000 0000 TW5 TW4 TW3 CLICK-CLICK time window Doc ID 17530 Rev 1 LIS3DH Ths2 Ths1 Ths0 TLI2 TLI1 TLI0 TLA2 TLA1 TLA0 TW2 TW1 TW0 ...
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... LIS3DH 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK trademark. Doc ID 17530 Rev 1 Package information ® www.st.com. 39/42 ...
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... LGA-16: Mechanical data Dim Figure 12. LGA-16: Mechanical data and package dimensions 40/42 mm Min. Typ. 0.785 0.2 2. 0.5 1 0.04 0.1 0.875 1.275 0.29 0.35 0.19 0.25 0.15 0.05 Doc ID 17530 Rev 1 LIS3DH Max. 1 3.15 3.15 1.06 2.06 0.16 0.41 0.31 7983231 ...
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... LIS3DH 10 Revision history Table 68. Document revision history Date 21-May-2010 Revision 1 Initial release Doc ID 17530 Rev 1 Revision history Changes 41/42 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 42/42 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 17530 Rev 1 LIS3DH ...