LIS3DH STMicroelectronics, LIS3DH Datasheet - Page 18

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LIS3DH

Manufacturer Part Number
LIS3DH
Description
Board Mount Accelerometers MEMS Ultra Low-Power 3-Axes Nano
Manufacturer
STMicroelectronics
Datasheet

Specifications of LIS3DH

Sensing Axis
X, Y, Z
Acceleration
16 g
Digital Output - Number Of Bits
16 bit
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.71 V
Supply Current
6 uA to 11 uA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Digital Output - Bus Interface
I2C, SPI
Mounting Style
SMD/SMT
Shutdown
Yes
Sensitivity
1 mg/digit to 12 mg/digit
Package / Case
LGA-16
Output Type
Digital
Acceleration Range
± 2g, ± 4g, ± 8g, ± 16g
No. Of Axes
3
Interface Type
I2C, SPI
Sensitivity Per Axis
12mg / Digit
Sensor Case Style
LGA
No. Of Pins
16
Supply Voltage Range
1.71V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Application hints
4
4.1
18/42
Application hints
Figure 5.
The device core is supplied through Vdd line while the I/O pads are supplied through
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF aluminum) should
be placed as near as possible to the pin 14 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to
without blocking the communication bus, in this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the I
The ADC1, ADC2 & ADC3 if not used can be left floating or keep connected to Vdd or GND.
The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be
completely programmed by the user through the I
Soldering information
The LGA package is compliant with the ECOPACK
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com.
Vdd
LIS3DH electrical connection
Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO
100nF
GND
10µF
2
C or SPI interfaces.When using the I
Figure
Vdd_IO
Doc ID 17530 Rev 1
5). It is possible to remove Vdd maintaining Vdd_IO
1
5
5
ADC1
16
6
TOP VIEW
2
ADC2
C/SPI interface.
®
, RoHS and “Green” standard.
14
8
13
9
9
2
C, CS must be tied high.
INT1
INT2
when I2C interface is used
Pull-up to be added
Vdd_IO
Rpu
ADC3
Rpu
LIS3DH

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