LPC1342FBD48,151 NXP Semiconductors, LPC1342FBD48,151 Datasheet - Page 4

• Manufacturer Part Number: LPC1342FBD48,151
• Description: IC MCU 32BIT 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FBD48,151

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: LPC1342
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, USB, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5214

NXP Semiconductors
5. Block diagram
LPC1311_13_42_43
Product data sheet
Fig 1.
DTR, DSR
(1) LPC1342/43 only.
(2) LQFP48 package only.
DCD
CT32B0_MAT[3:0]
CT32B1_MAT[3:0]
CT16B0_MAT[2:0]
CT16B1_MAT[1:0]
GPIO ports
CT32B0_CAP0
CT32B1_CAP0
CT16B0_CAP0
CT16B1_CAP0
PIO0/1/2/3
(2)
Block diagram
, RI
(2)
(2)
, CTS,
, RTS
RXD
TXD
HIGH-SPEED
GPIO
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
I-code
bus
CORTEX-M3
TEST/DEBUG
INTERFACE
SWD
UART
ARM
D-code
bus
All information provided in this document is subject to legal disclaimers.
slave
system
bus
Rev. 3 — 10 August 2010
AHB-LITE BUS
CONTROLLER
BRIDGE
AHB TO
USB DEVICE
USB PHY
APB
USB pins
slave
slave
(1)
(1)
LPC1311/13/42/43
SYSTEM CONTROL
WDO
POR
IRC
10-bit ADC
IOCONFIG
8/16/32 kB
I
32-bit ARM Cortex-M3 microcontroller
2
FLASH
C-BUS
WDT
SSP
LPC1311/13/42/43
slave
XTALOUT
POWER CONTROL,
slave
slave
GENERATION,
FUNCTIONS
clocks and
SYSTEM
XTALIN
CLOCK
controls
SRAM
4/8 kB
ROM
RESET
002aae722
© NXP B.V. 2010. All rights reserved.
CLKOUT
AD[7:0]
SCL
SDA
SCK
SSEL
MISO
MOSI
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