LPC2138FBD64/01,11 NXP Semiconductors, LPC2138FBD64/01,11 Datasheet - Page 13

• Manufacturer Part Number: LPC2138FBD64/01,11
• Description: IC ARM7 MCU FLASH 512K 64-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2138FBD64/01,11

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

NXP Semiconductors
6. Functional description
LPC2131_32_34_36_38
Product data sheet
6.1 Architectural overview
6.2 On-chip flash program memory
6.3 On-chip static RAM
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The LPC2131/32/34/36/38 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash
memory system respectively. This memory may be used for both code and data storage.
Programming of the flash memory may be accomplished in several ways. It may be
programmed In System via the serial port. The application program may also erase and/or
program the flash while the application is running, allowing a great degree of flexibility for
data storage field firmware upgrades, etc. When the LPC2131/32/34/36/38 on-chip
bootloader is used, 32/64/128/256/500 kB of flash memory is available for user code.
The LPC2131/32/34/36/38 flash memory provides a minimum of 100000 erase/write
cycles and 20 years of data-retention.
On-chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8-bit, 16-bit, and 32-bit. The LPC2131, LPC2132/34, and LPC2136/38
provide 8 kB, 16 kB and 32 kB of static RAM respectively.
•
•
The standard 32-bit ARM set.
A 16-bit Thumb set.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 February 2011
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
© NXP B.V. 2011. All rights reserved.
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