D2-45057-QR-T Intersil, D2-45057-QR-T Datasheet - Page 19

• Manufacturer Part Number: D2-45057-QR-T
• Description: IC DGTL AMP PWM CTRLR 68QFN
• Manufacturer: Intersil
• Series: D2Audio™r
• Type: Class Dr

Specifications of D2-45057-QR-T

• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 30W x 1 @ 8 Ohm
• Voltage - Supply: 9 V ~ 26 V
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Output Options
The D2-45057, D2-45157 devices provide four
configuration options for the power stage outputs. The
power stage configuration is selected by strapping the
OCFG0 and OCFG1 pins high or low. These defined
configurations include:
• 2 Channels of Full Bridge, 4-Quadrant Outputs,
• 2 Channels of Full Bridge, 2-Quadrant Outputs
• 4 Channels of Half-Bridge Outputs
• 2 Channels Half-Bridge, Plus 1 Channel Full Bridge
Audio processing routing and control supporting the
output stage configurations is defined by the logical high
or low strapping of the nERROR/CFG0 and PSSYNC/CFG1
pins. Audio path definition, audio path output routing,
and output stage configurations are automatically set to
one of the four available modes, based on these
configuration settings.
PWM Audio Outputs
Three PWM outputs provide audio for up to three
line-level outputs. Audio processing channel assignment
is mapped to these PWM outputs, based on the device’s
available configuration settings.
Using only a simple passive filter, the PWM outputs will
drive line-level outputs at a nominal 1V
addition of active filter configurations, these can also
drive headphone outputs, or 2V
outputs. (Alternately, these PWM outputs could also be
used to drive powered outputs, using additional power
stages on the system design.)
Control and Operation
Control Register Summary
The control interface provides access to the registers
used for audio processing blocks and signal flow
parameters. Audio input selection (I
receiver input) and all programmable data elements used
in the audio processing paths are controlled through
these register parameters, and each parameter is
defined with its specific register address. Programming
details, register identification, and parameter calculations
are provided in the DAE-4/DAE-4P Register API
Specification document.
I
The D2-45057, D2-45157 device includes a 2-Wire I
compatible interface for communicating with an external
controller. This interface is usable through either an
external microcontroller bus, or for communication to
EEPROMs, or other compatible peripheral chips.
The I
operation and is multi-master capable. In a D2-45057,
D2-45157 system application, it operates as an I
device, where the system controller operates as the
I
2
2
C master.
C 2-Wire Control Interface
2
C interface supports normal and fast mode
19
rms
or higher line
2
S input or S/PDIF
RMS
D2-45057, D2-45157
. With
2
C slave
2
C
Reading and Writing Control Registers
All reads or writes to registers (shown in Figures 14 and
15) begin with a Start Condition, followed by the Device
Address byte, three Register Address bytes, three Data
bytes and a Stop Condition.
Register writes through the I
setting the read/write bit that is within the device
address byte. Write sequence shown in Figure 14 is
described in Table 2.
All reads to registers, shown in Figure 15, require two
steps. First, the master must send a dummy write which
consist of sending a Start, followed by the device address
with the write bit set, and three register address bytes.
Then, the master must send a repeated Start, following
with the device address with the read/write bit set to
read, and then read the next three data bytes. The
master must Acknowledge (ACK) the first two read bytes
and send a Not Acknowledge (NACK) on the third byte
received and a Stop condition to complete the
transaction. The device's control interface acknowledges
each byte by pulling SDA low on the bit immediately
following each write byte. The read sequence shown in
Figure 15 is described in Table 3.
BYTE
BYTE
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
Device Address
Register Address [23:16] Upper 8 bits of address
Register Address [15:8]
Register Address [7:0]
Data[23:16]
Data[15:8]
Data[7:0]
Device Address
Register Address [23:16] Upper 8 bits of address
Register Address [15:8]
Register Address [7:0]
Device Address
Data[23:16]
Data[15:8]
Data[7:0]
TABLE 2. I
TABLE 3. I
NAME
NAME
2
2
C WRITE SEQUENCE
C READ SEQUENCE
2
C interface are initiated by
Device Address, With R/W
bit set
Middle 8 bits of address
Lower 8 bits of address
Upper 8 bits of write data
Middle 8 bits of write data
Lower 8 bits of write data
Device Address, With Write
bit set
Middle 8 bits of address
Lower 8 bits of address
Device Address, With Read
bit set
Upper 8 bits of write data
Middle 8 bits of write data
Lower 8 bits of write data
DESCRIPTION
DESCRIPTION
July 29, 2010
FN6785.0