IDT70V3319S133BF IDT, Integrated Device Technology Inc, IDT70V3319S133BF Datasheet
IDT70V3319S133BF
Specifications of IDT70V3319S133BF
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IDT70V3319S133BF Summary of contents
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... Features: True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access – Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) – Industrial: 4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode – Due to limited pin count PL/ FT option is not supported on the 128-pin TQFP package ...
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... High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Description: The IDT70V3319/ high-speed 256/128K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Pin Configuration (1,2,3,4,5) 08/01/ TDI NC A 17L TDO I ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Pin Configuration (1,2,3,4,5,8,9) 08/06/ 14L A 2 15L A 3 16L 17L ( DDQL ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Pin Names Left Port Right Port Chip Enables , , R/W R/W Read/Write Enable Output Enable L R ...
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... I/O ( (p+1) I/O , UB, LB and OE the rising edge of CLK, regardless of all other memory control signals including CE IL 6.42 6 Industrial and Commercial Temperature Ranges (1,2,3) Lower Byte I/O MODE 0-8 High-Z Deselected–Power Down High-Z Deselected–Power Down High-Z Both Bytes Deselected ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Recommended Operating Temperature and Supply Voltage Ambient Grade Temperature Commercial + Industrial - +85 C NOTES: 1. This is the ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM (1) Capacitance (T = +25° 1.0MH A Symbol Parameter Conditions C Input Capacitance IN (3) C Output Capacitance OUT NOTES: 1. These parameters are determined by device characterization, ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating DD L Current (Both Outputs Disabled, Ports Active ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM AC Test Conditions (V Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 50Ω DATA OUT Figure ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol t Clock Cycle Time (Flow-Through) CYC1 (1) t Clock Cycle Time (Pipelined) CYC2 t Clock High ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of Read Cycle for Pipelined Operation (2) (FT/PIPE = CH2 CLK ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of a Multi-Device Pipelined Read t CYC2 t t CH2 CL2 CLK ADDRESS (B1 0(B1) DATA OUT(B1) ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of Left Port Write to Pipelined Right Port Read CLK "A" R/W "A" ADDRESS "A" MATCH ...
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... CNTEN, and REPEAT = Addresses do not have to be accessed sequentially since ADS = V are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled) t CYC2 t t CH2 ...
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... Output state (High, Low, or High-impedance) is determined by the previous cycle control signals UB, LB, and ADS = V , CNTEN, and REPEAT = Addresses do not have to be accessed sequentially since ADS = V reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. CL1 ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN (2) Qx ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs) t CYC2 t CH2 CLK ADDRESS An (3) INTERNAL An ADDRESS t t SAD ...
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... LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asyn- chronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH LOW on CE for one clock cycle will power down 0 1 the internal circuitry to reduce static power consumption ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM JTAG Timing Specifications t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Identification Register Definitions Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) NOTE: 1. Device ID for IDT70V3399 is 0x0315. ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Ordering Information XXXXX A 999 A Device Power Speed Package Type NOTE: 1. Green parts available. For specific speeds, packages and powers contact your local sales office. IDT Clock Solution ...
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IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Datasheet Document History: 06/02/00: Initial Public Offering 07/12/00: Page 1 Added mux to functional block diagram 06/20/01: Page 1 Added JTAG information for TQFP package Page 4 Corrected TQFP package ...