X28HC64J-12 Intersil, X28HC64J-12 Datasheet - Page 13
![IC EEPROM 64KBIT 120NS 32PLCC](/photos/18/29/182917/x28hc64j-12_sml.jpg)
X28HC64J-12
Manufacturer Part Number
X28HC64J-12
Description
IC EEPROM 64KBIT 120NS 32PLCC
Manufacturer
Intersil
Datasheet
1.X28HC64D-12.pdf
(17 pages)
Specifications of X28HC64J-12
Format - Memory
EEPROMs - Parallel
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
120ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
32-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
X28HC64J-12
Manufacturer:
XICOR
Quantity:
3 198
Company:
Part Number:
X28HC64J-12
Manufacturer:
XICOR
Quantity:
5 510
Part Number:
X28HC64J-12
Manufacturer:
XICOR
Quantity:
20 000
Company:
Part Number:
X28HC64J-12T1
Manufacturer:
INTERSIL
Quantity:
4 219
Part Number:
X28HC64J-12TZ
Manufacturer:
INTERSIL
Quantity:
20 000
CE Controlled Write Cycle
Page Write Cycle
NOTES:
10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the
9. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch
DATA OUT
ADDRESS
data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
CE or WE controlled write cycle timing.
(NOTE 10)
DATA IN
(NOTE 9)
Address
WE
OE
CE
WE
OE
CE
I/O
*For each successive write within the page write operation, A
writes to an unknown address could occur.
t
WP
t
OES
13
t
AS
Byte 0
t
CS
t
DV
t
WPH
Byte 1
t
AH
t
BLC
t
CW
X28HC64
HIGH Z
Byte 2
t
DS
DATA VALID
t
OEH
6
Byte n
–A
t
WC
12
t
t
CH
DH
should be the same or
Byte n+1
Last Byte
Byte n+2
t
WC
August 28, 2009
FN8109.2