PC28F128P30B85E NUMONYX, PC28F128P30B85E Datasheet - Page 33
![IC FLASH 128MBIT 85NS 64EZBGA](/photos/7/29/72914/pc28f128p30b85_s_l9yq_sml.jpg)
PC28F128P30B85E
Manufacturer Part Number
PC28F128P30B85E
Description
IC FLASH 128MBIT 85NS 64EZBGA
Manufacturer
NUMONYX
Series
StrataFlash™r
Datasheet
1.RD48F4400P0VBQEJ.pdf
(97 pages)
Specifications of PC28F128P30B85E
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (8Mx16)
Speed
85ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
887046
887046
PC28F128P30B85 S L9YQ
887046
PC28F128P30B85 S L9YQ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PC28F128P30B85E
Manufacturer:
Micron Technology Inc
Quantity:
10 000
P30
Note:
8.4.4
8.5
8.6
August 2008
Order Number: 306666-12
proceeding.
Any spurious writes are ignored after a buffer fill operation and when internal program is
only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write
cycles should be issued to the device until SR[0] = 0 and the device is ready for the
next buffer fill.
The host programming system continues the BEFP algorithm by providing the next
group of data words to be written to the buffer. Alternatively, it can terminate this
phase by changing the block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the
device enters the BEFP Exit phase.
BEFP Exit Phase
When SR[7] is set, the device has returned to normal operating conditions. A full status
check should be performed at this time to ensure the entire block programmed
successfully. When exiting the BEFP algorithm with a block address change, the read
mode will not change. After BEFP exit, any valid command can be issued to the device.
Program Suspend
Issuing the Program Suspend command while programming suspends the
programming operation. This allows data to be accessed from the device other than the
one being programmed. The Program Suspend command can be issued to any device
address. A program operation can be suspended to perform reads only. Additionally, a
program operation that is running during an erase suspend can be suspended to
perform a read operation (see
page
When a programming operation is executing, issuing the Program Suspend command
requests the WSM to suspend the programming algorithm at predetermined points. The
device continues to output Status Register data after the Program Suspend command is
issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend
latency is specified in
To read data from the device, the Read Array command must be issued. Read Array,
Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid
commands during a program suspend.
During a program suspend, deasserting CE# places the device in standby, reducing
active current. V
unchanged while in program suspend. If RST# is asserted, the device is reset.
Program Resume
The Resume command instructs the device to continue programming, and
automatically clears Status Register bits SR[7,2]. This command can be written to any
address. If error bits are set, the Status Register should be cleared before issuing the
next instruction. RST# must remain deasserted (see
Resume Flowchart” on page
81).
PP
must remain at its programming level, and WP# must remain
Section 16.0, “Program and Erase Characteristics” on page
81).
Figure 35, “Program Suspend/Resume Flowchart” on
Figure 35, “Program Suspend/
Datasheet
67.
33