PC28F128P30B85E NUMONYX, PC28F128P30B85E Datasheet - Page 45

• Manufacturer Part Number: PC28F128P30B85E
• Description: IC FLASH 128MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F128P30B85E

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 887046; 887046; PC28F128P30B85 S L9YQ

P30
Table 21: WAIT Functionality Table (Sheet 2 of 2)
11.2.4
Figure 15: Data Hold Timing
11.2.5
August 2008
Order Number: 306666-12
All Asynchronous Reads
All Writes
Notes:
1.
2.
Data Hold
Data Hold
Active: WAIT is asserted until data becomes valid, then deasserts
When OE# = V
1 CLK
2 CLK
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output
remains valid on DQ[15:0] for one or two clock cycles. This period of time is called the
“data cycle”. When DH is set, output data is held for two clocks (default). When DH is
cleared, output data is held for one clock (see
time and the flash memory’s clock-to-data output delay should be considered when
determining whether to hold output data for one or two clocks. A method for
determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
t
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock. If t
2 clock periods must be used.
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle
before valid data (default). When WD is cleared, WAIT is deasserted during valid data.
CHQV
IH
= 20 ns and t
during writes, WAIT = High-Z
D[15:0] [Q]
D[15:0] [Q]
t
t
20 ns + 4 ns
DATA
CHQV (ns) +
CLK [C]
Condition
= Data set up to Clock (defined by CPU)
DATA
t
DATA
≤
CHQV (ns) +
25 ns
= 4 ns. Applying these values to the formula above:
(ns)
Output
Valid
≤
One CLK Period (ns)
t
DATA
Output
Valid
(ns) > One CLK Period (ns), data hold setting of
Deasserted
High-Z
Output
Valid
Figure
15). The processor’s data setup
Output
Valid
WAIT
Output
Valid
Notes
Datasheet
1,2
1
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