PC28F128P30B85E NUMONYX, PC28F128P30B85E Datasheet - Page 57
![IC FLASH 128MBIT 85NS 64EZBGA](/photos/7/29/72914/pc28f128p30b85_s_l9yq_sml.jpg)
PC28F128P30B85E
Manufacturer Part Number
PC28F128P30B85E
Description
IC FLASH 128MBIT 85NS 64EZBGA
Manufacturer
NUMONYX
Series
StrataFlash™r
Datasheet
1.RD48F4400P0VBQEJ.pdf
(97 pages)
Specifications of PC28F128P30B85E
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (8Mx16)
Speed
85ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
887046
887046
PC28F128P30B85 S L9YQ
887046
PC28F128P30B85 S L9YQ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PC28F128P30B85E
Manufacturer:
Micron Technology Inc
Quantity:
10 000
P30
Table 30: AC Read Specifications for 64/128- Mbit Densities (Sheet 2 of 2)
Table 31: AC Read Specifications for 256/512-Mbit Densities (Sheet 1 of 3)
August 2008
Order Number: 306666-12
R108
R111
Clock Specifications
R200
R201
R202
R203
Synchronous Specifications
R301
R302
R303
R304
R305
R306
R307
R311
R312
Notes:
1.
2.
3.
4.
5.
6.
7.
Asynchronous Specifications
R1
R2
Num
Num
See
allowable input slew rate.
OE# may be delayed by up to t
Sampled, not 100% tested.
Address hold in synchronous burst mode is t
Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package .
Synchronous read mode is not supported with TTL level inputs.
Applies only to subsequent synchronous reads.
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
APA
phvh
CLK
CLK
CH/CL
FCLK/RCLK
AVCH/L
VLCH/L
ELCH/L
CHQV / tCLQV
CHQX
CHAX
CHTV
CHVL
CHTX
AVAV
AVQV
Figure 18, “AC Input/Output Reference Waveform” on page 55
Symbol
Symbol
Page address access
RST# high to ADV# high
CLK frequency
CLK period
CLK high/low time
CLK fall/rise time
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
CLK Valid to ADV# Setup
WAIT Hold from CLK
Read cycle time
Address to output valid
(5,6)
Parameter
ELQV
– t
GLQV
Parameter
after CE#’s falling edge without impact to t
CHAX
or t
VHAX
, whichever timing specification is satisfied first.
V
V
V
V
256/512-Mb TSOP
packages
V
V
V
V
256/512-Mb TSOP
packages
CC
CC
CC
CC
= 1.8 V
= 1.7 V
= 1.8 V
= 1.7 V
Speed
– 2.0
– 2.0
– 2.0
– 2.0
TSOP
TSOP
Min
19.2
Min
85
88
95
30
25
10
-
-
-
5
9
9
9
3
3
3
-
-
-
-
-
-
for timing measurements and max
ELQV.
Max
Max
85
88
95
25
52
40
17
17
-
-
3
-
-
-
-
-
-
-
-
-
-
-
Unit
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Datasheet
1,3,5,6
Notes
Notes
1,4,7
1,7
1,7
1,7
1
1
1
57