PCA85132U/2DB/Q1,0 NXP Semiconductors, PCA85132U/2DB/Q1,0 Datasheet - Page 21

• Manufacturer Part Number: PCA85132U/2DB/Q1,0
• Description: IC LCD DRIVER 32 UNCASED
• Manufacturer: NXP Semiconductors

Specifications of PCA85132U/2DB/Q1,0

• Display Type: LCD
• Configuration: Multiple
• Interface: I²C
• Digits Or Characters: Any Digit Type
• Current - Supply: 60µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 95°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
2.
PCA85132_1
Product data sheet
For further information, please consider the NXP application note:
7.16.1.1 START and STOP conditions
7.16.1 Bit transfer
By connecting pin SDAACK to pin SDA on the PCA85132, the SDA line becomes fully
I
pin to the system SDA line can be significant, possibly a voltage divider is generated by
the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a
consequence it may be possible that the acknowledge generated by the PCA85132 can’t
be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle
is required, it is therefore necessary to minimize the track resistance from the SDAACK
pin to the system SDA line to guarantee a valid LOW level.
By separating the acknowledge output from the serial data line (having the SDAACK open
circuit) design efforts to generate a valid acknowledge level can be avoided. However, in
that case the I
acknowledge cycle.
The following definition assumes SDA and SDAACK are connected and refers to the pair
as SDA.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are shown in
2
Fig 12. Bit transfer
Fig 13. Definition of START and STOP conditions
C-bus compatible. In COG applications where the track resistance from the SDAACK
SDA
SCL
2
START condition
C-bus master has to be set up in such a way that it ignores the
All information provided in this document is subject to legal disclaimers.
SDA
SCL
2
S
Rev. 01 — 6 May 2010
data valid
Ref. 1
data line
stable;
“AN10170”.
Figure
allowed
change
of data
12).
LCD driver for low multiplex rates
Figure
STOP condition
mba607
PCA85132
P
13.
© NXP B.V. 2010. All rights reserved.
mbc622
SDA
SCL
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