IDTTS3000B3ANRG IDT, Integrated Device Technology Inc, IDTTS3000B3ANRG Datasheet - Page 6

• Manufacturer Part Number: IDTTS3000B3ANRG
• Description: IC TEMP SENSOR DGTL 8DFN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDTTS3000B3ANRG

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Control Logic, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -20°C ~ 125°C
• Output Type: 2-Wire Serial, I²C™/SMBUS™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC Characteristics
1. For a RESTART condition, or following a write cycle.
2. Guaranteed by design and characterization, not necessarily tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between falling edge of SCL and the falling or
4. The TS3000B3A does not initiate clock stretching which is an optional I
5. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval
exceeds the value of t
within or after the current data byte in the transfer process. Devices that have detected this condition must reset their
communication and be able to receive a new START condition no later than t
the host controller and embedded controller and most devices that can master the SMBus. Some devices do not contain a clock
low drive circuit; this simple kind of device typically may reset its communications port after a start or stop condition. A
timeout condition can only be ensured if the device that is forcing the timeout holds SCL low for t
6. The temperature sensor family of devices are not required to support the SMBus ALERT function.
Clock Frequency
Clock Pulse Width High Time
Clock Pulse Width Low Time
Detect clock low timeout, Capabilities
Register bit 6 =1
SDA Rise Time
SDA Fall Time
Data In Setup Time
Data In Hold Time
Data Out Hold Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
Time Between Stop Condition and Next
Start Condition
Write Time
rising edge of SDA.
Parameter
TIMEOUT,MIN
. After the master in a transaction detects this condition, it must generate a stop condition
t
Symbol
t
TIMEOUT
t
t
t
t
SU:STA
HD:DAT
t
SU:DAT
HD:STA
t
SU:STO
t
LOW
HD:DI
f
t
HIGH
t
BUF
SCL
t
t
R
F
W
2
2
5
1
6
6 of 21
Min.
1300
1300
600
100
200
600
600
600
10
25
20
0
V
DD
> 2.2 V
Max.
400
300
300
900
35
10
2
C bus feature
TIMEOUT,MAX
Units
kHz
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
. Typical device examples include
TIMEOUT,MAX
May 12, 2010
or longer.