OM13008,598 NXP Semiconductors, OM13008,598 Datasheet
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LPC122x 32-bit ARM Cortex-M0 microcontroller 128 kB flash and 8 kB SRAM Rev. 1.2 — 29 March 2011 1. General description The LPC122x extend NXP's 32-bit ARM microcontroller continuum and target a wide range of industrial applications in ...
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... NXP Semiconductors Crystal oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz Internal RC (IRC) oscillator trimmed accuracy that can optionally be used as a system clock. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. ...
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... NXP Semiconductors Digital peripherals Micro DMA controller with 21 channels. CRC engine. Two UARTs with fractional baud rate generation and internal FIFO. One UART with RS-485 and modem support and one standard UART with IrDA. SSP/SPI controller with FIFO and multi-protocol capabilities. ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name Description LPC1227FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1226FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1225FBD64/321 LQFP64 LQFP64: plastic low profile quad flat package ...
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... NXP Semiconductors 5. Block diagram LPC122x TEST/DEBUG CORTEX-M0 HIGH-SPEED GPIO ports SCK SSEL MISO MOSI RXD0 TXD0 UART0 RS-485 DTR0, DSR0, CTS0, DCD0, RI0, RTS0 RXD1 TXD1 SCL SDA 4 × MAT 32-bit COUNTER/TIMER 0 4 × CAP 4 × MAT 32-bit COUNTER/TIMER 1 4 × CAP 2 × ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning XTALIN XTALOUT VREF_CMP PIO0_19 PIO0_20 PIO0_21 PIO0_22 PIO0_23 PIO0_24 SWDIO/PIO0_25 SWCLK/PIO0_26 (1) PIO0_27 PIO2_12 PIO2_13 PIO2_14 PIO2_15 (1) High-current output driver. Remark: For a full listing of all functions for each pin see Fig 2. Pin configuration LQFP64 package LPC122X ...
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... NXP Semiconductors XTALIN XTALOUT VREF_CMP PIO0_19 PIO0_20 PIO0_21 PIO0_22 PIO0_23 PIO0_24 SWDIO/PIO0_25 SWCLK/PIO0_26 PIO0_27 (1) High-current output driver. Remark: For a full listing of all functions for each pin see Fig 3. Pin configuration LQFP48 package LPC122X Objective data sheet LPC122x (1) 12 Table 3. All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6.2 Pin description All pins except the supply pins can have more than one function as shown in pin function is selected through the pin’s IOCON register in the IOCONFIG block. The multiplexed functions (see UART receive, transmit, and control functions, and the serial wire debug functions. ...
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... NXP Semiconductors Table 3. LPC122x pin description Symbol PIO0_7/CTS0 CT32B1_CAP1/ CT32B1_MAT1 PIO0_8/RXD1 CT32B1_CAP2/ CT32B1_MAT2 PIO0_9/TXD1 CT32B1_CAP3/ CT32B1_MAT3 PIO0_10/SCL 25 37 PIO0_11/SDA CT16B0_CAP0/ CT16B0_MAT0 PIO0_12/CLKOUT CT16B0_CAP1/ CT16B0_MAT1 RESET/PIO0_13 28 40 PIO0_14/SCK 29 41 PIO0_15/SSEL CT16B1_CAP0/ CT16B1_MAT0 PIO0_16/MISO CT16B1_CAP1/ CT16B1_MAT1 LPC122X Objective data sheet …continued Start Type Reset ...
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... NXP Semiconductors Table 3. LPC122x pin description Symbol PIO0_17/MOSI 32 44 PIO0_18/SWCLK CT32B0_CAP0/ CT32B0_MAT0 PIO0_19/ACMP0_I0 CT32B0_CAP1/ CT32B0_MAT1 PIO0_20/ACMP0_I1 CT32B0_CAP2/ CT32B0_MAT2 PIO0_21/ACMP0_I2 CT32B0_CAP3/ CT32B0_MAT3 PIO0_22/ACMP0_I3 7 7 PIO0_23 ACMP1_I0/ CT32B1_CAP0/ CT32B1_MAT0 PIO0_24/ACMP1_I1 CT32B1_CAP1/ CT32B1_MAT1 SWDIO/ACMP1_I2 CT32B1_CAP2/ CT32B1_MAT2/ PIO0_25 SWCLK/ACMP1_I3 CT32B1_CAP3/ CT32B1_MAT3/ PIO0_26 LPC122X Objective data sheet … ...
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... NXP Semiconductors Table 3. LPC122x pin description Symbol PIO0_27/ACMP0_O 12 12 PIO0_28/ACMP1_O CT16B0_CAP0/ CT16B0_MAT0 PIO0_29/ROSC CT16B0_CAP1/ CT16B0_MAT1 R/PIO0_30/AD0 34 46 R/PIO0_31/AD1 35 47 PIO1_0 to PIO1_6 R/PIO1_0/AD2 36 48 R/PIO1_1/AD3 37 49 PIO1_2/SWDIO/AD4 38 50 PIO1_3/AD5/WAKEUP 39 51 PIO1_4/AD6 40 52 LPC122X Objective data sheet …continued Start Type Reset Description logic ...
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... NXP Semiconductors Table 3. LPC122x pin description Symbol PIO1_5/AD7 CT16B1_CAP0/ CT16B1_MAT0 PIO1_6 CT16B1_CAP1/ CT16B1_MAT1 PIO2_0 to PIO2_15 PIO2_0 CT16B0_CAP0/ CT16B0_MAT0/ RTS0 PIO2_1 CT16B0_CAP1/ CT16B0_MAT1/RXD0 PIO2_2 CT16B1_CAP0/ CT16B1_MAT0/TXD0 PIO2_3 CT16B1_CAP1/ CT16B1_MAT1/DTR0 PIO2_4 CT32B0_CAP0/ CT32B0_MAT0/CTS0 PIO2_5 CT32B0_CAP1/ CT32B0_MAT1/RI0 LPC122X Objective data sheet …continued Start Type Reset ...
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... NXP Semiconductors Table 3. LPC122x pin description Symbol PIO2_6 CT32B0_CAP2/ CT32B0_MAT2/DCD0 PIO2_7 CT32B0_CAP3/ CT32B0_MAT3/DSR0 PIO2_8 CT32B1_CAP0/ CT32B1_MAT0 PIO2_9 CT32B1_CAP1/ CT32B1_MAT1 PIO2_10 CT32B1_CAP2/ CT32B1_MAT2/TXD1 PIO2_11 CT32B1_CAP3/ CT32B1_MAT3/RXD1 PIO2_12/RXD1 - 13 PIO2_13/TXD1 - 14 PIO2_14 - 15 PIO2_15 - 16 RTCXIN 46 58 RTCXOUT 45 57 XTALIN 1 1 XTALOUT 2 2 VREF_CMP 3 3 LPC122X Objective data sheet … ...
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... NXP Semiconductors Table 3. LPC122x pin description Symbol DD(IO DD(3V3 SSIO [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled. [2] 3.3 V tolerant, digital I/O pin; default: pull-up enabled, no hysteresis. 2 [3] I C-bus pins tolerant; open-drain; default: no pull-up/pull-down; no hysteresis. ...
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... NXP Semiconductors Table 4. Peripheral CT16B0 CT16B1 CT32B0 CT32B1 UART0 UART1 SSP/SPI I2C LPC122X Objective data sheet Pin multiplexing Function CT16B0_CAP0 CT16B0_CAP1 CT16B0_MAT0 CT16B0_MAT1 CT16B1_CAP0 CT16B1_CAP1 CT16B1_MAT0 CT16B1_MAT1 CT32B0_CAP0 CT32B0_CAP1 CT32B0_CAP2 CT32B0_CAP3 CT32B0_MAT0 CT32B0_MAT1 CT32B0_MAT2 CT32B0_MAT3 CT32B1_CAP0 CT32B1_CAP1 CT32B1_CAP2 CT32B1_CAP3 CT32B1_MAT0 CT32B1_MAT1 ...
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... NXP Semiconductors Table 4. Peripheral SWD Reset Clockout pin [1] After reset, the SWD functions are selected by default on pins PIO0_26 and PIO0_25. 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex- general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. ...
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... NXP Semiconductors LPC122x 4 GB reserved private peripheral bus reserved AHB peripherals reserved APB peripherals 1 GB reserved 8 kB boot ROM reserved 8 kB custom ROM reserved 16 kB NXP library ROM reserved 8 kB SRAM (LPC1225/6/ SRAM (LPC1224) reserved 128 kB on-chip flash (LPC1227/301 on-chip flash (LPC1226/301) ...
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... NXP Semiconductors • In the LPC122x, the NVIC supports 32 vectored interrupts. In addition the individual GPIO inputs are NVIC-vector capable. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation. • Non-maskable Interrupt (NMI) can be programmed to use any of the peripheral interrupts ...
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... NXP Semiconductors • Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers. • Supports multiple DMA cycle types and multiple DMA transfer widths. • Performs all DMA transfers using the single AHB-Lite burst type. 7.8 CRC engine The Cyclic Redundancy Check (CRC) engine with programmable polynomial settings supports several CRC standards commonly used ...
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... NXP Semiconductors 7.10.1 Features • 16-byte Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. ...
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... NXP Semiconductors • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ...
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... NXP Semiconductors • Comparator outputs connect to two timers, allowing for the recording of comparison event time stamps. 7.15 General purpose external event counter/timers The LPC122x includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...
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... NXP Semiconductors • Selectable time period from (T multiples of T • The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator (IRC) or the Watchdog oscillator. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability ...
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... NXP Semiconductors IRC oscillator watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator SYSPLLCLKSEL Fig 5. LPC122x clocking generation block diagram 7.18.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU ...
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... NXP Semiconductors The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency the maximum CPU operating frequency, by the system PLL. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. 7.18.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin ...
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... NXP Semiconductors In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses ...
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... NXP Semiconductors An external pull-up resistor is required on the RESET pin if Deep power-down mode is used. 7.19.3 Brownout detection The LPC122x includes four levels for monitoring the voltage on the V voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt ...
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... NXP Semiconductors 7.20 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug is supported. 7.21 Integer division routines The LPC122x contain performance-optimized integer division routines with support for up to 32-bit width in the numerator and denominator. Routines for signed and unsigned division and division with remainder are available ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V input/output supply voltage DD(IO) V input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature ...
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... NXP Semiconductors 9. Thermal characteristics 9.1 Thermal characteristics The average chip junction temperature, T equation amb • T amb • R th(j-a) • The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications. ...
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... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V input/output supply DD(IO) voltage V supply voltage (3.3 V) DD(3V3) I supply current DD Standard port pins, RESET I LOW-level input IL current I HIGH-level input IH current I OFF-state output OZ current V input voltage ...
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... NXP Semiconductors Table 7. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V LOW-level input IL voltage V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I HIGH-level OHS short-circuit output current I LOW-level OLS short-circuit output ...
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... NXP Semiconductors Table 7. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Oscillator pins V crystal input voltage i(xtal) V crystal output voltage o(xtal) Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [1] [2] Including voltage on outputs in 3-state mode ...
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... NXP Semiconductors 10.1 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of < ...
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... NXP Semiconductors (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 6. (mA) Fig 7. LPC122X Objective data sheet <tbd> C; active mode entered executing code Conditions: T amb peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks disabled ...
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... NXP Semiconductors (mA) Fig 8. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 9. LPC122X Objective data sheet −40 −15 Conditions 3.3 V; active mode entered executing code DD(3V3) peripherals enabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>). ...
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... NXP Semiconductors (μA) Fig 10. Deep-sleep mode: Typical supply current I Fig 11. Deep power-down mode: Typical supply current I LPC122X Objective data sheet 3.6 V DD(3V3) 3 −40 −15 Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG =<tbd>). supply voltages V ...
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... NXP Semiconductors 10.3 Electrical pin characteristics Fig 12. High-drive output: Typical HIGH-level output voltage V Fig 13. I LPC122X Objective data sheet <tbd> Conditions 3.3 V. DD(IO) output current ( <tbd> Conditions 3.3 V. DD(IO) 2 C-bus pins (high current sink): Typical LOW-level output current I LOW-level output voltage V OL All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors Fig 14. Typical LOW-level output current I Fig 15. Typical HIGH-level output voltage V LPC122X Objective data sheet <tbd> Conditions 3.3 V. DD(IO ( <tbd> Conditions 3.3 V. DD(IO All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 29 March 2011 32-bit ARM Cortex-M0 microcontroller ...
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... NXP Semiconductors Fig 16. Typical pull-up current I LPC122X Objective data sheet <tbd> Conditions 3.3 V. DD(IO) versus input voltage V pu All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 29 March 2011 32-bit ARM Cortex-M0 microcontroller 001aab173 (X) I LPC122x © NXP B.V. 2011. All rights reserved. ...
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... NXP Semiconductors 10.4 ADC characteristics Table 9. amb 3.6 V. Symbol L(adj c(ADC) Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [1] voltages. [2] Conditions: V [3] The ADC is monotonic, there are no missing codes. [4] The differential linearity error (E See ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC122X Objective data sheet ...
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... NXP Semiconductors 10.5 BOD static characteristics Table 10 amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC122x user manual. LPC122X Objective data sheet [1] BOD static characteristics C. Parameter Conditions threshold voltage interrupt level 1 ...
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... NXP Semiconductors 11. Dynamic characteristics 11.1 Flash memory Table 11. amb Symbol prog N endu t ret [1] Erase and programming times are valid over the lifetime of the device (minimum 20000 cycles). [2] Number of program/erase cycles. 11.2 External clock Table 12. amb Symbol f osc T cy(clk) t CHCX ...
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... NXP Semiconductors 11.3 Internal oscillators Table 13. amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. f osc(RC) (MHz) Fig 19. Internal RC oscillator frequency versus temperature Table 14. ...
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... NXP Semiconductors Table 15. Dynamic characteristic: I [ +85 C. amb Symbol Parameter t fall time f t LOW period of the SCL clock LOW t HIGH period of the SCL clock HIGH t data hold time HD;DAT t data set-up time SU;DAT [1] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors SDA SCL SCL 2 Fig 20. I C-bus pins clock timing LPC122X Objective data sheet t SU;DAT HD;DAT LOW All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 29 March 2011 LPC122x 32-bit ARM Cortex-M0 microcontroller t VD;DAT t HIGH © NXP B.V. 2011. All rights reserved. ...
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... NXP Semiconductors 11.5 SSP/SPI interface Table 16. Dynamic characteristics: SSP pins in SPI mode amb Symbol Parameter T clock cycle time cy(clk) SSP master t data set-up time DS t data hold time DH t data output valid time v(Q) t data output hold time h(Q) SSP slave ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 21. SSP master timing in SPI mode LPC122X Objective data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 29 March 2011 ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 22. SSP slave timing in SPI mode LPC122X Objective data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 29 March 2011 ...
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... NXP Semiconductors 12. Application information 12.1 XTAL input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional ...
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... NXP Semiconductors 12.3 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for the LPC1227FBD64/301 in Table 17 3 Parameter Input clock: IRC (12 MHz) maximum peak level IEC level Input clock: crystal oscillator (12 MHz) maximum peak level ...
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... NXP Semiconductors 13. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT313-2 136E05 Fig 25 ...
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... NXP Semiconductors 14. Abbreviations Table 18. Acronym ADC AHB APB BOD CCITT CRC DMA FIFO GPIO I/O IrDA IRC JEDEC PLL SPI SSI SSP UART LPC122X Objective data sheet Abbreviations Description Analog-to-Digital-Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection Comité Consultatif International Téléphonique et Télégraphique ...
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... NXP Semiconductors 15. Revision history Table 19. Revision history Document ID Release date LPC122X v.1.2 20110329 Modifications: LPC122X v.1.1 20110221 Modifications: LPC122X v.1 20110214 LPC122X Objective data sheet Data sheet status Objective data sheet • Figure 2 “Pin configuration LQFP64 package” RTCXOUT changed to 57. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: LPC122X Objective data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 16 7.1 ARM Cortex-M0 processor . . . . . . . . . . . . . . . 16 7.1.1 System tick timer . . . . . . . . . . . . . . . . . . . . . . 16 7.2 On-chip flash program memory . . . . . . . . . . . 16 7 ...
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... NXP Semiconductors 17 Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 32-bit ARM Cortex-M0 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC122x All rights reserved ...