LIS35DETR STMicroelectronics, LIS35DETR Datasheet - Page 18

• Manufacturer Part Number: LIS35DETR
• Description: IC ACCELEROMETER 3AXIS 14LGA
• Manufacturer: STMicroelectronics

Specifications of LIS35DETR

• Axis: X, Y, Z
• Acceleration Range: ±2.3g, 9.2g
• Sensitivity: 18mg/digit, 72mg/digit
• Voltage - Supply: 2.16 V ~ 3.6 V
• Output Type: Digital
• Bandwidth: 100Hz ~ 400Hz Selectable
• Interface: I²C, SPI
• Mounting Type: Surface Mount
• Package / Case: 14-LGA
• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 8 g
• Digital Output - Number Of Bits: 8 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.16 V
• Supply Current: 0.3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Digital Output - Bus Interface: I2C, SPI
• Mounting Style: SMD/SMT
• Shutdown: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Digital interfaces
5.1.1
18/39
I
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LIS35DE is 001110xb. SDO pad can be used to
modify less significant bit of the device address. If SDO pad is connected to voltage supply
LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’
(address 0011100b). This solution permits to connect and address two different
accelerometer to the same I
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data has
been received.
The I
protocol must be adhered to. After the start condition (ST) a salve address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address is transmitted: the 7 LSb
represent the actual register address while the MSB enables address auto increment. If the
MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow
multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the Master will transmits to the slave with direction unchanged.
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 10.
Table 11.
2
C operation
Master
Slave
Command
2
C embedded inside the LIS35DE behaves like a slave device and the following
Read
Read
Write
Write
SAD+Read/Write patterns
Transfer when Master is writing one byte to slave
ST
SAD[6:1]
001110
001110
001110
001110
SAD + W
2
C lines.
Doc ID 15594 Rev 1
SAK
SAD[0] = SDO
0
0
1
1
SUB
SAK
R/W
0
1
0
1
Table 10
DATA
explains how the
00111011 (3Bh)
00111010 (3Ah)
00111001 (39h)
00111000 (38h)
SAD+R/W
SAK
LIS35DE
SP