LIS35DETR STMicroelectronics, LIS35DETR Datasheet - Page 27

• Manufacturer Part Number: LIS35DETR
• Description: IC ACCELEROMETER 3AXIS 14LGA
• Manufacturer: STMicroelectronics

Specifications of LIS35DETR

• Axis: X, Y, Z
• Acceleration Range: ±2.3g, 9.2g
• Sensitivity: 18mg/digit, 72mg/digit
• Voltage - Supply: 2.16 V ~ 3.6 V
• Output Type: Digital
• Bandwidth: 100Hz ~ 400Hz Selectable
• Interface: I²C, SPI
• Mounting Type: Surface Mount
• Package / Case: 14-LGA
• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 8 g
• Digital Output - Number Of Bits: 8 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.16 V
• Supply Current: 0.3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Digital Output - Bus Interface: I2C, SPI
• Mounting Style: SMD/SMT
• Shutdown: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LIS35DE
7.3
7.4
Table 21.
CTRL_REG3 [interrupt CTRL register] (22h)
Table 22.
Table 23.
Table 24.
HP_FILTER_RESET (23h)
Dummy register. Reading at this address zeroes instantaneously the content of the internal
high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0g.
This allows to overcome the settling time of the high pass filter.
IHL
PP_OD
I2CFG2
I2CFG1
I2CFG0
I1CFG2
I1CFG1
I1CFG0
IHL
I1(2)_CFG2
HP_coeff2,1
10
11
0
0
0
0
1
1
High pass filter cut-off frequency configuration (continued)
CTRL_REG3 [interrupt CTRL register] (22h) register
CTRL_REG3 [interrupt CTRL register] (22h) register description
Data signal on Int pad control bits
PP_OD
Interrupt active high, low. Default value 0.
(0: active high; 1: active low)
Push-pull/Open Drain selection on interrupt pad. Default value 0.
(0: push-pull; 1: open drain)
Data Signal on Int2 pad control bits. Default value 000.
(see table below)
Data Signal on Int1 pad control bits. Default value 000.
(see table below)
I1(2)_CFG1
I2CFG2
0
0
1
1
0
1
Doc ID 15594 Rev 1
(DR=100 Hz)
ft (Hz)
I2CFG1
0.25
0.5
I1(2)_CFG0
I2CFG0
0
1
0
1
0
1
I1CFG2
FF_WU_1 OR FF_WU_2
(DR=400 Hz)
Click interrupt
Register description
Data Ready
Int1(2) pad
FF_WU_1
FF_WU_2
I1CFG1
ft (Hz)
GND
2
1
I1CFG0
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