LAN9215-MT SMSC, LAN9215-MT Datasheet - Page 79
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LAN9215-MT
Manufacturer Part Number
LAN9215-MT
Description
CONTROLLER, ENET, NON-PCI, 100TQFP
Manufacturer
SMSC
Specifications of LAN9215-MT
Data Rate
100Mbps
No. Of Ports
2
Ethernet Type
IEEE 802.3 / 802.3u
Supply Current
40mA
Supply Voltage Range
2.97V To 3.63V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
TQFP
Interface Type
HBI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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Quantity:
450
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LAN9215-MT
Manufacturer:
Standard
Quantity:
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Company:
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Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX
SMSC LAN9215
5.3.7
31:30
29-28
27-16
14-13
BITS
12-8
7-0
15
[31]
0
0
1
1
RX End Alignment. This field specifies the alignment that must be
maintained on the last data transfer of a buffer. The LAN9215 will add
extra DWORDs of data up to the alignment specified in the table below.
The host is responsible for removing these extra DWORDs. This
mechanism can be used to maintain cache line alignment on host
processors.
Please refer to
Note:
Reserved
RX DMA Count (RX_DMA_CNT). This 12-bit field indicates the amount
of data, in DWORDS, to be transferred out of the RX data FIFO before
asserting the RXD_INT. After being set, this field is decremented for each
DWORD of data that is read from the RX data FIFO. This field can be
overwritten with a new value before it reaches zero.
Force RX Discard (RX_DUMP). This self-clearing bit clears the RX data
and status FIFOs of all pending data. When a ‘1’ is written, the RX data
and status pointers are cleared to zero.
Note:
Reserved
RX Data Offset (RXDOFF). This field controls the offset value, in bytes,
that is added to the beginning of an RX data packet. The start of the valid
data will be shifted by the number of bytes specified in this field. An offset
of 0-31 bytes is a valid number of offset bytes.
Note:
Reserved
RX_CFG—Receive Configuration Register
This register controls the LAN9215receive engine.
Offset:
The desired RX End Alignment must be set before reading a
packet. The RX end alignment can be changed between reading
receive packets, but must not be changed if the packet is
partially read.
Please refer to section “Force Receiver Discard (Receiver
Dump)” on page 58 for a detailed description regarding the use
of RX_DUMP.
The two LSBs of this field (D[9:8]) must not be modified while
the RX is running. The receiver must be halted, and all data
purged before these two bits can be modified. The upper three
bits (DWORD offset) may be modified while the receiver is
running. Modifications to the upper bits will take affect on the
next DWORD read.
[30]
0
1
0
1
Table 5.2
Table 5.2 RX Alignment Bit Definitions
for bit definitions
DESCRIPTION
6Ch
DATASHEET
79
Size:
16-byte alignment
32-byte alignment
4-byte alignment
End Alignment
Reserved
32 bits
TYPE
R/W
R/W
R/W
RO
SC
RO
RO
Revision 1.2 (03-29-06)
DEFAULT
00000
000h
00b
0
-
-
-