LAN9218-MT SMSC, LAN9218-MT Datasheet - Page 31

• Manufacturer Part Number: LAN9218-MT
• Description: CONTROLLER, ENET, 10/100, 100TQFP
• Manufacturer: SMSC

Specifications of LAN9218-MT

• Data Rate: 100Mbps
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Supply Current: 40mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• Interface Type: HBI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC
3.7
3.8
3.8.1
Word Swap Mode - Word Swap Register equal to 0xFFFFFFFF
LAN9218
ADDRESS
A1 PIN
The General Purpose Timer is a programmable block that can be used to generate periodic host
interrupts. The resolution of this timer is 100uS.
The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting
down when the TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from
set ‘1’ to cleared ‘0,’ the GPT_CNT field is initialized to FFFFh. The GPT_CNT register is also initialized
to FFFFh on a reset. Software can write the pre-load value into the GPT_LOAD field at any time; e.g.,
before or after the TIMER_EN bit is asserted. The GPT Enable bit TIMER_EN is located in the
GPT_CFG register.
Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is
written to the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT
interrupt status bit and the IRQ signal if the GPT_INT_EN bit is set, and continues counting. The GPT
interrupt status bit is in the INT_STS Register. The GPT_INT hardware interrupt can only be set if the
GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only
be cleared by writing a ‘1’ to the bit.
The LAN9218 can optionally load its MAC address from an external serial EEPROM. If a properly
configured EEPROM is detected by the LAN9218 at power-up, hard reset or soft reset, the ADDRH
and ADDRL registers will be loaded with the contents of the EEPROM. If a properly configured
EEPROM is not detected, it is the responsibility of the host LAN Driver to set the IEEE addresses.
The LAN9218 EEPROM controller also allows the host system to read, write and erase the contents
of the Serial EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for
128 x 8-bit operation.
MAC Address Auto-Load
On power-up, hard reset or soft reset, the EEPROM controller attempts to read the first byte of data
from the EEPROM (address 00h). If the value A5h is read from the first address, then the EEPROM
controller will assume that an external Serial EEPROM is present. The EEPROM controller will then
access the next EEPROM byte and send it to the MAC Address register byte 0 (ADDRL[7:0]). This
process will be repeated for the next five bytes of the MAC Address, thus fully programming the 48-
bit MAC address. Once all six bytes have been programmed, the “MAC Address Loaded” bit is set in
the E2P_CMD register. A detailed explanation of the EEPROM byte ordering with respect to the MAC
address is given in
If an 0xA5h is not read from the first address, the EEPROM controller will end initialization. It is then
the responsibility of the host LAN driver software to set the IEEE address by writing to the MAC’s
ADDRH and ADDRL registers.
General Purpose Timer (GP Timer)
EEPROM Interface
A1 = 0
A1 = 1
Table 3.7 Word Swap Control (continued) (16-bit mode only)
D[15:8]
Byte 3
Byte 1
Section 5.4.3, "ADDRL—MAC Address Low Register," on page
BYTE ORDER
DATASHEET
Byte 2
Byte 0
D[7:0]
31
When A1=0, D[15:0] is mapped to the high order
words of CSRs and FIFOs. When A1=1, D[15:0] is
mapped to the low order words of CSRs and FIFOs.
In this case A1=1 data will always precede A1=0
data.
DESCRIPTION
Revision 1.93 (11-27-07)
100.