SCC2692AC1N28 NXP Semiconductors, SCC2692AC1N28 Datasheet - Page 25

• Manufacturer Part Number: SCC2692AC1N28
• Description: IC, DUAL UART FIFO 115.2KBPS 5.5V DIP-28
• Manufacturer: NXP Semiconductors

Specifications of SCC2692AC1N28

• No. Of Channels: 2
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Max: 5.5V
• Supply Voltage Min: 4.5V
• Data Rate: 1Mbps
• Uart Features: Parity, Framing & Overrun Detection, False Start Bit Detection, Line Break Detection & Generation
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
1998 Sep 04
Dual asynchronous receiver/transmitter (DUART)
A condition that occurs infrequently has been observed where the receiver will ignore all data. It is caused by a corruption of the start bit
generally due to noise. When this occurs the receiver will appear to be asleep or locked up. The receiver must be reset for the UART to
continue to function properly.
Reset in the Normal Mode (Receiver Enabled)
Recovery can be accomplished easily by issuing a receiver software reset followed by a receiver enable. All receiver data, status and
programming will be preserved and available before reset. The reset will NOT affect the programming.
Reset in the Wake-Up Mode (MR1[4:3] = 11)
Recovery can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software
reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and available before
reset. The reset will NOT affect the programming.
The receiver has a digital filter designed to reject “noisy” data transitions and the receiver state machine was designed to reject noisy start
bits or noise that might be considered a start bit. In spite of these precautions, corruption of the start bit can occur in 15ns window
approximately 100ns prior to the rising edge of the data clock. The probability of this occurring is less than 10
A corrupted start bit may have some deleterious effects in ASYNC operation if it occurs within a normal data block. The receiver will tend
to align its data clock to the next ‘0’ bit in the data stream, thus potentially corrupting the remainder of the data block. A good design
practice, in environments where start bit corruption is possible, is to monitor data quality (framing error, parity error, break change and
received break) and “data stopped” time out periods. Time out periods can be enabled using the counter/timer in the SCC2691, SCC2692,
SCC2698B and SC68692 products. This monitoring can indicate a potential start bit corruption problem.
25
–5
at 9600 baud.
Product specification
SCC2692
SD00097