74HC573N NXP Semiconductors, 74HC573N Datasheet - Page 2

• Manufacturer Part Number: 74HC573N
• Description: IC, 74HC CMOS LOGIC
• Manufacturer: NXP Semiconductors

Specifications of 74HC573N

• Latch Type: Transparent
• Output Current: 7.8mA
• Propagation Delay: 14ns
• No. Of Bits: 8
• Supply Voltage Range: 2V To 6V
• Logic Case Style: DIP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +125°C
• Svhc: No SVHC
• Ic Output Type: Tri State Non Inverted
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
SYMBOL
t
C
C
PHL/
Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessors
Useful as input or output port for
microprocessors/microcomputers
3-state non-inverting outputs for
bus oriented applications
Common 3-state output enable
input
Functionally identical to the “563”
and “373”
Output capability: bus driver
I
Octal D-type transparent latch; 3-state
I
PD
CC
f
C
i
“74HC/HCT/HCU/HCMOS Logic Package Information”
PD
= input frequency in MHz; f
L
t
category: MSI
(C
PLH
= output load capacitance in pF; V
P
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
2
= 25 C; t
V
f
o
PARAMETER
propagation delay
input capacitance
power dissipation capacitance per latch notes 1 and 2
CC
) = sum of outputs
D
LE to Q
2
n
to Q
f
r
i
= t
+ (C
n
n
I
f
= GND to V
= 6 ns
o
L
= output frequency in MHz
V
CC
GENERAL DESCRIPTION
The 74HC/HCT573 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT573 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and 3-state outputs for bus oriented
applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.
The “573” consists of eight D-type
transparent latches with 3-state true
outputs. When LE is HIGH, data at
CC
2
CC
= supply voltage in V
f
; for HCT the condition is V
o
) where:
2
.
CONDITIONS
C
D
L
= 15 pF; V
in W):
I
= GND to V
CC
= 5 V
the D
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.
The “573” is functionally identical to
the “563” and “373”, but the “563” has
inverted outputs and the “373” has a
different pin arrangement.
CC
n
HC
14
15
3.5
26
inputs enter the latches. In this
1.5 V
TYPICAL
74HC/HCT573
Product specification
HCT
17
15
3.5
26
UNIT
ns
ns
pF
pF