F25L004A-100PIG ELITE SEMICONDUCTOR, F25L004A-100PIG Datasheet
F25L004A-100PIG
Specifications of F25L004A-100PIG
Related parts for F25L004A-100PIG
F25L004A-100PIG Summary of contents
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... F25L004A –50PAIG 50MHz SOIC GENERAL DESCRIPTION The F25L004A is a 4Megablt, 3V only CMOS Serial Flash memory device organized as 512K bytes of 8 bits. This device is packaged in 8-lead SOIC 200mil. ESMT’s memory devices reliably store memory data even after 100,000 program and erase cycles. ...
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... ESMT PIN CONFIGURATIONS 8-PIN SOIC VSS 4 8-PIN PDIP VSS 4 Elite Semiconductor Memory Technology Inc. Operation Temperature condition -40 8 VDD HOLD 7 SCK VDD HOLD 7 SCK Publication Date: Oct. 2007 Revision: F25L004A ° C ° C ~85 1.1 2/32 ...
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... To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. F25L004A ° C ~85 Publication Date: Oct. 2007 Revision: 1.1 3/32 ° ...
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... ESMT SECTOR STRUCTURE Table1 : F25L004A Sector Address Table Sector Size Sector (Kbytes) Block 127 4KB 112 4KB 111 4KB 4KB 95 4KB 4KB 79 4KB 4KB 63 4KB 4KB 47 4KB 4KB 31 4KB 4KB 15 4KB 4KB Elite Semiconductor Memory Technology Inc. Operation Temperature condition -40 Block Address ...
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... ESMT Table2 : F25L004A Block Protection Table TOP Protection Level BP2 0 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks All Blocks All Blocks Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Program or Erase) operations ...
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... FUNTIONAL BLOCK DIAGRAM Address Buffers and Latches CE Elite Semiconductor Memory Technology Inc. X-Decoder Y-Decoder I/O Butters Control Logic Data Latches Serial Interface SCK SO WP HOLD SI F25L004A Operation Temperature condition -40 Flash and Publication Date: Oct. 2007 Revision: 1.1 ° C ° C ~85 6/32 ...
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... ctive Figure 1 : HOLD CONDITION WAVEFORM Write Protection F25L004A provides software Write protection. The Write Protect pin ( WP ) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description ...
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... Chip-Erase instruction completion • Write-Status-Register instructions Elite Semiconductor Memory Technology Inc. Operation Temperature condition -40 the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Function F25L004A ° C ~85 Default at Read/Write Power- ...
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... ESMT Instructions Instructions are used to Read, Write (Erase and Program), and configure the F25L004A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, instructions, the Write-Enable (WREN) instruction must be executed first ...
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... The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A low for the duration of the Read cycle. See Figure 2 for the Read sequence ADD. ADD. ADD. MSB N D OUT MSB F25L004A Operation Temperature condition - must remain active N+1 N+2 N+3 N+4 D ...
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... ADD. ADD. ADD. X MSB MSB F25L004A is reached, the address N+1 N+2 N+3 N ...
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... Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 4 for the Byte-Program sequence ADD. ADD. MSB HIGH IMPENANCE Operation Temperature condition - Following the address, the data ADD MSB LSB Publication Date: Oct. 2007 Revision: F25L004A ° C ° C ~85 1.1 12/32 ...
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... FIGURE 5 : ENABLE SO AS HARDWARE DURING AAI PROGRAMMING Elite Semiconductor Memory Technology Inc. Operation Temperature condition - Following the addresses, two bytes of data is input sequentially FIGURE 6 : DISABLE SO AS HARDWARE DURING AAI PROGRAMMING F25L004A ° Refer to End-of-Write with A =1. CE must be driven The hardware end of write detection BP. ...
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... ESMT FIGURE 7 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETETION FIGURE 8 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETETION Elite Semiconductor Memory Technology Inc. F25L004A Operation Temperature condition -40 Publication Date: Oct. 2007 Revision: 1.1 ° C ° C ~85 ...
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... The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See Figure 9 for the Block-Erase sequence. Publication Date: Oct. 2007 Revision: F25L004A ° C ° C ~85 = Most Significant address) ...
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... TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 10 for the Sector-Erase -A ]. Address bits sequence ADD. ADD. MSB MSB HIGH IMPENANCE F25L004A Operation Temperature condition -40 = Most Significant address) are used to determine MS ), remaining address bits can be VIL ADD. Publication Date: Oct. 2007 Revision: 1.1 ° C ° ...
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... See Figure 12 for the RDSR instruction sequence Bit7 MSB Operation Temperature condition -40 for the completion of the internal self-timed remain low until the status Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Status Register Out Publication Date: Oct. 2007 Revision: F25L004A ° C ° C ~85 data is read. 1.1 17/32 ...
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... CE must be driven high before the WRDI instruction is executed. Figure 14 : WRITE DISABLE (WRDI) SEQUENCE Elite Semiconductor Memory Technology Inc MODE3 SCK MODE0 06 SI MSB HIGH IMPENANCE MODE3 SCK MODE0 04 SI MSB HIGH IMPENANCE SO F25L004A Operation Temperature condition -40 Publication Date: Oct. 2007 Revision: 1.1 ° C ° C ~85 18/32 ...
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... WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0 ;BP1 and BP2 bits at the same time. See Table 3 for a summary description of WP and BPL functions 1011 12 13 1415 MSB HIGH IMPENANCE F25L004A Operation Temperature condition -40 ) prior to the low-to-high transition of the IH STATUS REGISTER Publication Date: Oct ...
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... Max Units =0 µ µA V =GND µA V OUT 0 =100 µ -0.2 0 =-100 µ Parameter Description F25L004A Operation Temperature condition -40 Test Conditions /0.9 V @33 MHz, SO=open VIN Max =GND Max Min DD =V Max DD =V Min Min DD DD Minimum 10 10 Test Condition ...
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... MODE3 0 1 SCK MODE1 SI MSB HIGH IMPENANCE SO Figure 16 : Read-Electronic-Signature (RES) Elite Semiconductor Memory Technology Inc Bit7 MSB Operation Temperature condition - Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Status Register Out Publication Date: Oct. 2007 Revision: F25L004A ° C ° C ~85 1.1 21/32 ...
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... ESMT JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as F25L004A and the manufacturer as ESMT. The device information can be read from executing the 8-bit command,.9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, 8CH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, BFH, identifies the manufacturer as ESMT. Byte2, 20H (for TOP), 21H (for BOTTOM),identifies the memory type as SPI Flash ...
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... ESMT Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L004A and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Following the Read-ID instruction, the manufacturer’ ...
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... Normal 33MHz Fast 50 MHz Fast 100 MHz VDD=2.7~3.6V VDD=2.7~3.6V VDD=3.0~3.6V Min Max Min Max Min 100 100 100 F25L004A ° C ° ~85 Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 Max Units 100 MHz Publication Date: Oct. 2007 Revision: 1.1 24/32 C ...
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... Tested, Excludes external system level over head. 2.Typical values measured at 25°C, 3V. 3.Maximum values measured at 85°C, 2.7V. Elite Semiconductor Memory Technology Inc. Operation Temperature condition -40 Limits Unit Typ.(2) Max.(3) 60 120 300 12 100 100,000 - Cycles 20 - Years F25L004A ° Publication Date: Oct. 2007 Revision: 1.1 25/32 ° C ...
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... ESMT FIGURE 19: SERIAL INPUT TIMING DIAGRAM FIGURE 20: SERIAL OUTPUT TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L004A Operation Temperature condition -40 Publication Date: Oct. 2007 Revision: 1.1 ° C ° C ~85 26/32 ...
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... ESMT FIGURE 21: HOLD TIMING DIAGRAM FIGURE 22: POWER-UP TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L004A Operation Temperature condition -40 Publication Date: Oct. 2007 Revision: 1.1 ° C ° C ~85 27/32 ...
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... FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS FIGURE 24: A TEST LOAD EXAMPLE Elite Semiconductor Memory Technology Inc. 0.7VCC AC Measurement Level 0.3VCC Note : Input pulse rise and fall time are <5ns F25L004A Operation Temperature condition -40 Output timing reference level 0.5VCC Publication Date: Oct. 2007 Revision: 1.1 ° C ° ...
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... BSC 0.050 BSC 1.00 1.05 1.10 0.039 0.041 ° 0 ° 0 ° 8 --- Publication Date: Oct. 2007 Revision: F25L004A ° C ° C ~85 L1 Max 0.197 0.157 0.050 0.043 ° 8 --- 1.1 29/32 ...
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... BSC 0.050 BSC 1.27 1.37 1.47 0.050 0.054 ° 0 ° 0 ° 8 --- Publication Date: Oct. 2007 Revision: F25L004A ° C ° C ~85 Max 0.319 0.212 0.032 0.058 ° 8 --- 1.1 30/32 ...
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... Dimension in inch Min Norm Max 0.21 0.015 0.125 0.130 0.135 0.355 0.365 0.400 0.300 BSC. 0.245 0.250 0.255 0.115 0.130 0.150 0.100 TYP. 0.335 0.355 0.375 0.018 TYP. 0.060 TYP Publication Date: Oct. 2007 Revision: F25L004A ° C ° C ~85 1.1 31/32 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Operation Temperature condition -40 Important Notice F25L004A ° C ~85 Publication Date: Oct. 2007 Revision: 1 ...