f25l004a Elite Semiconductor Memory Technology Inc., f25l004a Datasheet
f25l004a
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f25l004a Summary of contents
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... F25L004A -50PAG 50MHz SOIC GENERAL DESCRIPTION The F25L004A Megabit 3V only CMOS Serial Flash memory device. ESMT’s memory devices reliably store memory data even after 100,000 program and erase cycles. The F25L004A features a sector erase architecture. The device memory array is divided into 128 uniform sectors with 4K byte each ...
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... ESMT PIN CONFIGURATIONS 8-PIN SOIC VSS 4 8-PIN PDIP VSS 4 Elite Semiconductor Memory Technology Inc. 8 VDD HOLD 7 SCK VDD HOLD 7 SCK Publication Date: Jan. 2009 Revision: 1.6 F25L004A 2/30 ...
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... Pin Name SCK Serial Clock SI Serial Data Input SO Serial Data Output Chip Enable CE Write Protect WP Hold HOLD VDD Power Supply VSS Ground SECTOR STRUCTURE Table1 : F25L004A Sector Address Table Sector Size Sector Block (Kbytes) 127 4KB 112 4KB 111 4KB ...
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... ESMT Table2 : F25L004A Block Protection Table Protection Level BP2 0 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks All Blocks All Blocks Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Program or Erase) operations ...
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... ctive Figure 1 : HOLD CONDITION WAVEFORM Write Protection F25L004A provides software Write protection. The Write Protect pin ( WP ) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 2 for Block-Protection description ...
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... Chip-Erase instruction completion • Write-Status-Register instructions Elite Semiconductor Memory Technology Inc. the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Function F25L004A Default at Read/Write Power- ...
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... ESMT Instructions Instructions are used to Read, Write (Erase and Program), and configure the F25L004A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, instructions, the Write-Enable (WREN) instruction must be executed first ...
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... The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A low for the duration of the Read cycle. See Figure 2 for the Read sequence ADD. ADD. ADD. MSB N D OUT MSB F25L004A - must remain active N+1 N+2 N+3 N ...
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... ADD. ADD. ADD. X MSB MSB F25L004A is reached, the address N+1 N+2 N+3 N ...
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... Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 4 for the Byte-Program sequence ADD. ADD. MSB HIGH IMPENANCE F25L004A -A ]. Following the address, the data ADD. D ...
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... DURING AAI PROGRAMMING Elite Semiconductor Memory Technology Inc Following the addresses, two bytes of data is input sequentially FIGURE 6 : DISABLE SO AS HARDWARE DURING AAI PROGRAMMING F25L004A . Refer to End-of-Write with A =1. CE must be driven The hardware end of write detection BP. ...
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... ESMT FIGURE 7 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETETION FIGURE 8 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETETION Elite Semiconductor Memory Technology Inc. F25L004A Publication Date: Jan. 2009 Revision: 1.6 12/30 ...
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... VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See Figure 9 for the Block-Erase sequence. Publication Date: Jan. 2009 Revision: 1.6 F25L004A = Most Significant address) ), remaining X 13/30 ...
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... Sector-Erase cycle. See Figure 10 for the Sector-Erase -A ]. Address bits sequence ADD. ADD. MSB MSB HIGH IMPENANCE F25L004A = Most Significant address) are used to determine MS ), remaining address bits can be VIL ADD. Publication Date: Jan. 2009 Revision: 1.6 14/30 ...
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... Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE See Figure 12 for the RDSR instruction sequence Bit7 MSB F25L004A for the completion of the internal self-timed remain low until the status ...
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... CE must be driven high before the WRDI instruction is executed. Figure 14 : WRITE DISABLE (WRDI) SEQUENCE Elite Semiconductor Memory Technology Inc MODE3 SCK MODE0 06 SI MSB HIGH IMPENANCE MODE3 SCK MODE0 04 SI MSB HIGH IMPENANCE SO F25L004A Publication Date: Jan. 2009 Revision: 1.6 16/30 ...
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... BP0 ;BP1 and BP2 bits at the same time. See Table 3 for a summary description of WP and BPL functions HIGH IMPENANCE F25L004A ) prior to the low-to-high transition of the 1011 12 13 1415 STATUS ...
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... After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 13H, identifies the device as F25L004A. The instruction sequence is shown in Figure17. The JEDEC Read ID instruction is terminated by a low to high transition any time during data output other command is ...
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... Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L004A and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Following the Read-ID instruction, the manufacturer’ ...
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... Units =0 µ µ µ Parameter F25L004A Unit V °C Test Conditions /0.9 V @33 MHz, SO=open VIN =GND Max =GND Max OUT ...
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... F25L004A Test Condition Maximum OUT Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 Units Min Max 100 MHz 5 ns ...
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... V Elite Semiconductor Memory Technology Inc. Limits Symbol Typ.(2) Max.(3) 90 200 100 100,000 20 . DD(min) F25L004A Unit Cycles - Years Publication Date: Jan. 2009 Revision: 1.6 22/30 ...
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... ESMT FIGURE 19: SERIAL INPUT TIMING DIAGRAM FIGURE 20: SERIAL OUTPUT TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L004A Publication Date: Jan. 2009 Revision: 1.6 23/30 ...
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... ESMT CE SCK SO SI HOLD FIGURE 21: HOLD TIMING DIAGRAM FIGURE 22: POWER-UP TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L004A Publication Date: Jan. 2009 Revision: 1.6 24/30 ...
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... FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS FIGURE 24: A TEST LOAD EXAMPLE Elite Semiconductor Memory Technology Inc. 0.7VCC AC Measurement Level 0.3VCC Note : Input pulse rise and fall time are <5ns F25L004A Output timing reference level 0.5VCC Publication Date: Jan. 2009 Revision: 1.6 25/30 ...
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... D 0.004 0.006 0.010 E 0.049 0.057 0.061 L 0.013 0.016 0.020 e 0.0075 0.008 0.010 L 1 θ 0.228 0.236 0.244 F25L004A GAUGE PLANE L DETAIL "X" "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 4.80 4.90 5.00 0.189 0.193 3.80 3.90 4.00 0.150 0.154 0.40 0.66 1.27 ...
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... E 0.002 0.006 0.010 E 1 0.067 0.071 0.075 L 0.014 0.016 0.020 e 0.007 0.008 0.010 L 1 θ 0.202 0.206 0.210 F25L004A L L1 DETAIL "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 7.70 7.90 8.10 0.303 0.311 5.18 5.28 5.38 0.204 0.208 0.50 0.65 0.80 0.020 0.026 1 ...
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... D 0.004 0.006 0.010 E 0.049 0.057 0.061 L 0.013 0.016 0.020 e 0.0075 0.008 0.010 L 1 θ 0.228 0.236 0.244 F25L004A GAUGE PLANE L DETAIL "X" "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 4.80 4.90 5.00 0.189 0.193 3.80 3.90 4.00 0.150 0.154 0.40 0.66 0.86 ...
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... Elite Semiconductor Memory Technology Inc. Date Original 2006.09.27 1. Add AAI function. 2006.11.28 2. Delete speed grade 75MHz. 3. Modify ISB spec. Correct Ordering Information from F25L004A-50P to 2007.03.06 F25L004A-50D 1. Correct Byte Program Time. 2007.04.04 2. Modify ordering information. 1. Add “All Pb-free products are RoHS-Compliant” in the description of features 2008 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice F25L004A Publication Date: Jan. 2009 Revision: 1.6 30/30 ...