f25l004a Elite Semiconductor Memory Technology Inc., f25l004a Datasheet - Page 7

• Manufacturer Part Number: f25l004a
• Description: 3v Only 4 Mbit Serial Flash Memory
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Instructions
Instructions are used to Read, Write (Erase and Program), and
configure the F25L004A. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Auto Address Increment (AAI)
programming,
instructions, the Write-Enable (WREN) instruction must be
executed first. The complete list of the instructions is provided in
Table 5. All instructions are synchronized off a high to low
transition of CE . Inputs will be accepted on the rising edge of
TABLE 5: DEVICE OPERATION INSTRUCTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
Elite Semiconductor Memory Technology Inc.
Read
High-Speed-Read
Sector-Erase
Block-Erase
Chip-Erase
Byte-Program
Auto-Address-Increment-word
programming (AAI)
Read-Status-Register
(RDSR)
Enable-Write-Status-Register
(EWSR)
Write-Status-Register
(WRSR)
Write-Enable (WREN)
Write-Disable (WRDI)
Read-Electronic-Signature
(RES)
Jedec-Read-ID (JEDEC-ID)
Read-ID (RDID)
Enable SO to output RY/BY#
Status during AAI (EBSY)
Disable SO to output RY/BY#
Status during AAI (DBSY)
Operation: S
X = Dummy Input Cycles (V
One bus cycle is eight clock periods.
Sector addresses: use AMS-A12, remaining addresses can be V
Prior to any Byte-Program, Sector-Erase, Block-Erase,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be
programmed.
The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
Operation
8
8
Cycle Type/
5
5
4,5
(64K Byte)
5
Sector-Erase,
IN
(4K Byte)
= Serial In, S
1,2
6
11
9
10
OUT
IL
Block-Erase,
or V
100
33
50
Freq
= Serial Out
Max
MHz
MHz
MHz
IH
); - = Non-Applicable Cycles (Cycles are not necessary)
ADH Hi-Z A
D8H
C7H
ABH Hi-Z
0BH
9FH
(A0=0)
(A0=1)
03H
20H
60H
02H
05H
50H
01H
06H
04H
90H
90H
70H
80H
S
IN
or
1
S
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z
Hi-Z A
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z A
Hi-Z
Hi-Z
OUT
Chip-Erase
Data
23
23
23
23
23
23
23
S
X
X
X
-A
-A
-A
-A
-
-A
-A
-
-
-
-A
-
-
IN
16
16
16
16
16
16
16
2
D
S
8CH
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z
Hi-Z A
12H
OUT
OUT
-
-
-
-
-
-
IL
SCK starting with the most significant bit. CE must be driven
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first
or V
15
15
15
15
15
15
15
S
X
IH
-
-
-
-
-
-
-
-
-
IN
-A
-A
-A
-A
-A
-A
-A
Bus Cycle
8
8
8
8
8
8
8
3
Note
S
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
20H
Hi-Z A
OUT
-
-
-
-
-
-
-
-
7
S
7
7
7
7
7
7
7
X
-.
-A
-A
-A
-A
-
-A
-A
-
-
-
-
-
-A
-
-
IN
0
0
0
0
0
0
0
4
Note
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z D
Hi-Z D
13H
Hi-Z
OUT
-
-
-
-
-
-
-
-
Publication Date: Jan. 2009
Revision: 1.6
7
S
X
X
X
IN
-
-
-
-
-
-
-
-
-
-
-
-
IN
IN
0 Hi-Z D
5
Note
D
S
8CH
Hi-Z
12H
OUT
OUT
X
-
-
-
-
-
-
-
-
-
-
-
7
F25L004A
S
X
X
IN
-
-
-
-
-
-
-
-
-
-
-
IN
1 Hi-Z
6
D
S
8CH
12H
OUT
OUT
-
-
-
-
-
-
-
-
-
-
-
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