m24l416256sa Elite Semiconductor Memory Technology Inc., m24l416256sa Datasheet
m24l416256sa
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m24l416256sa Summary of contents
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... Ultra low standby power • Automatic power-down when deselected • CMOS for optimum speed/power Functional Description The M24L416256SA is a high-performance CMOS Pseudo static RAM organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. ...
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... A16 A15 A14 A11 A13 A12 M24L416256SA Publication Date: Jul. 2008 Revision: 1.4 2/14 ...
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... Typical values are included for reference only and are not guaranteed or tested. Typical values are measured 25°C. A Elite Semiconductor Memory Technology Inc. Operating, I Speed (ns MHz Max. Typ.[5] Max M24L416256SA Power Dissipation (mA) CC Standby fmax Typ.[5] Max. Typ.[ Publication Date: Jul. 2008 Revision: 1.4 (µ ...
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... 3.6V CC Test conditions methods and procedures for measuring thermal impedance, per EIA/JESD51. Test Conditions T = 25° MHz CC(typ) M24L416256SA Ambient Temperature ( −25°C to +85°C −40°C to +85°C -55, 60, 70 Min. Typ.[5] Max. 2.7 3.0 V – 0 ...
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... I CC(typ.) M24L416256SA Unit Ω Ω Ω V –70 Unit Min. Max ...
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... Notes: 15.Device is continuously selected 16 HIGH for Read Cycle. Elite Semiconductor Memory Technology Inc. –55 Min. Max. Min M24L416256SA –60 –70 Max. Min. Max Publication Date: Jul. 2008 Revision: 1.4 6/14 Unit ...
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... Chip Enable goes INACTIVE with 19.During this period in the DATA I/O waveform, the I/Os could be in the output state and input signals should not be applied. Elite Semiconductor Memory Technology Inc the output remains in a high-impedance state. IH M24L416256SA Publication Date: Jul. 2008 Revision: 1.4 7/14 ...
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... ESMT Switching Waveforms (continued) Write Cycle Controlled, OE LOW)[18, 19] Write Cycle 4 ( BHE / BLE Controlled, OE LOW)[18, 19] Elite Semiconductor Memory Technology Inc. M24L416256SA Publication Date: Jul. 2008 Revision: 1.4 8/14 ...
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... Address Avoidable Timing Address Avoidable Timing Address Elite Semiconductor Memory Technology Inc. ) one time at least shown as in Avoidable Timing 2. RC ≧15μ s ＜ ≧15μ ≧ RC ≧15μ s ＜ M24L416256SA t ≧ RC Publication Date: Jul. 2008 Revision: 1.4 9/14 ...
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... Speed (ns) Ordering Code 55 M24L416256SA-55BEG 60 M24L416256SA-60BEG 70 M24L416256SA-70BEG 55 M24L416256SA-55TEG 60 M24L416256SA-60TEG 70 M24L416256SA-70TEG 55 M24L416256SA-55BIG 60 M24L416256SA-60BIG 70 M24L416256SA-70BIG 55 M24L416256SA-55TIG 60 M24L416256SA-60TIG 70 M24L416256SA-70TIG Note : 20 Logic HIGH Logic LOW Don’t Care. Elite Semiconductor Memory Technology Inc. Inputs/Outputs X High Z H High Z L Data Out (I/O –I Data Out (I/O –I/O ) ...
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... ESMT Package Diagram 48-ball VFBGA ( mm) Elite Semiconductor Memory Technology Inc. M24L416256SA Publication Date: Jul. 2008 Revision: 1.4 11/14 ...
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... REF 11.96 0.455 0.463 10.29 0.395 0.400 0.69 0.016 0.023 0.031 REF 0.0315 BSC ° 8 ° 0 M24L416256SA Max 0.047 0.006 0.042 0.018 0.016 0.008 0.006 0.730 0.471 0.4 0.027 ° 8 Publication Date: Jul. 2008 Revision: 1.4 12/14 ...
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... Date 2007.07.04 Original 2007.09.10 Modify Vcc (max) =3.3V to 3.6V 1. Add 44-pin TSOPII package 2008.02.27 2. Add Avoid timing 2008.03.24 Add I-grade for TSOPII package 1. Move Revision History to the last 2008.07.04 2. Add Industrial grade for BGA package M24L416256SA Description Publication Date: Jul. 2008 Revision: 1.4 13/14 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M24L416256SA Publication Date: Jul. 2008 Revision: 1.4 14/14 ...