f25l016a Elite Semiconductor Memory Technology Inc., f25l016a Datasheet
f25l016a
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f25l016a Summary of contents
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... F25L016A –100PAG 100MHz 8 lead SOIC GENERAL DESCRIPTION The F25L016A is a 16Megablt, 3V only CMOS Serial Flash memory device organized as 2M bytes of 8 bits. This device is packaged in 8-lead SOIC 200mil. ESMT’s memory devices reliably store memory data even after 100,000 program and erase cycles ...
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... Data is shifted out on the falling edge of SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. F25L016A Publication Date: Jul. 2008 Revision: 1.4 2/32 ...
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... ESMT SECTOR STRUCTURE Table1 : F25L016A Sector Address Table Sector Size Sector Block (Kbytes) 511 4KB 496 4KB 495 4KB 480 4KB 479 4KB 464 4KB 463 4KB 448 4KB 447 4KB 432 4KB 431 4KB 416 4KB 415 4KB 400 4KB ...
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... F25L016A Block Address A17 A16 ...
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... F25L016A ...
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... ESMT Table2 : F25L016A Block Protection Table Protection Level BP2 0 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Program or Erase) operations. The ...
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... ESMT FUNTIONAL BLOCK DIAGRAM Address Buffers and Latches CE Elite Semiconductor Memory Technology Inc. X-Decoder Y-Decoder I/O Butters Control Logic Data Latches Serial Interface SCK HOLD F25L016A Flash and Publication Date: Jul. 2008 Revision: 1.4 7/32 ...
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... ctive Figure 1 : HOLD CONDITION WAVEFORM Write Protection F25L016A provides software Write protection. The Write Protect pin ( WP ) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description ...
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... Chip-Erase instruction completion • Write-Status-Register instructions Elite Semiconductor Memory Technology Inc. the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Function F25L016A Default at Read/Write Power- ...
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... ESMT Instructions Instructions are used to Read, Write (Erase and Program), and configure the F25L016A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5 ...
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... The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A low for the duration of the Read cycle. See Figure 2 for the Read sequence ADD. ADD. ADD. MSB N D OUT MSB F25L016A - must remain active N+1 N+2 N+3 N ...
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... ADD. ADD. ADD. X MSB MSB F25L016A is reached, the address N+1 N+2 N+3 N ...
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... Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 4 for the Byte-Program sequence ADD. ADD. MSB HIGH IMPENANCE F25L016A -A ]. Following the address, the data ADD. D ...
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... DURING AAI PROGRAMMING Elite Semiconductor Memory Technology Inc Following the addresses, two bytes of data is input sequentially FIGURE 6 : DISABLE SO AS HARDWARE DURING AAI PROGRAMMING F25L016A . Refer to End-of-Write with A =1. CE must be driven The hardware end of write detection BP. ...
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... ESMT FIGURE 7 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETETION FIGURE 8 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETETION Elite Semiconductor Memory Technology Inc. F25L016A Publication Date: Jul. 2008 Revision: 1.4 15/32 ...
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... VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See Figure 9 for the Block-Erase sequence. Publication Date: Jul. 2008 Revision: F25L016A = Most Significant address) ), remaining X 1.4 16/32 ...
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... Sector-Erase cycle. See Figure 10 for the Sector-Erase -A ]. Address bits sequence DD. ADD. MSB HIGH IMPENANCE F25L016A ] (A = Most Significant address) are used to determine remaining address bits can be VIL DD. Publication Date: Jul. 2008 Revision: 1.4 ...
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... Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE See Figure 12 for the RDSR instruction sequence Bit7 MSB F25L016A for the completion of the internal self-timed remain low until the status ...
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... CE must be driven high before the WRDI instruction is executed. Figure 14 : WRITE DISABLE (WRDI) SEQUENCE Elite Semiconductor Memory Technology Inc MODE3 SCK MODE0 06 SI MSB HIGH IMPENANCE MODE3 SCK MODE0 04 SI MSB HIGH IMPENANCE SO F25L016A Publication Date: Jul. 2008 Revision: 1.4 19/32 ...
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... BP0 ;BP1 and BP2 bits at the same time. See Table 3 for a summary description of WP and BPL functions 1011 12 13 1415 MSB HIGH IMPENANCE F25L016A ) prior to the low-to-high transition of the IH STATUS REGISTER Publication Date: Jul ...
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... µA V OUT 0 =100 µ -0.2 0 =-100 µ Parameter Description F25L016A Test Conditions /0.9 V @33 MHz, SO=open VIN Max =GND Max Min DD =V Max ...
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... Erase, Program or WRSR cycle is in progress is no decoded, and has no effect on the cycle in progress. CE MODE3 0 1 SCK MODE1 SI MSB HIGH IMPENANCE SO Figure 16 : Read-Electronic-Signature (RES) Elite Semiconductor Memory Technology Inc Bit7 MSB F25L016A Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Status Register Out Publication Date: Jul. 2008 Revision: 1.4 22/32 ...
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... After that, a 16-bit device ID is shifted out on the SO pin. Byte1, BFH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 15H, identifies the device as F25L016A. The instruction sequence is shown in Figure16. The JEDEC Read ID instruction is terminated by a low to high transition any time during data output other command is ...
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... ESMT Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L016A and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Following the Read-ID instruction, the manufacturer’ ...
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... F25L016A Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 Max Min Max Units 75 100 MHz 100 ...
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... Tested, Excludes external system level over head. 2.Typical values measured at 25°C, 3V. 3.Maximum values measured at 85°C, 2.7V. Elite Semiconductor Memory Technology Inc. Limits Unit Typ.(2) Max.(3) 90 200 100 100,000 - Cycles 20 - Years F25L016A Publication Date: Jul. 2008 Revision: 1.4 26/32 ...
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... ESMT FIGURE 19: SERIAL INPUT TIMING DIAGRAM FIGURE 20: SERIAL OUTPUT TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L016A Publication Date: Jul. 2008 Revision: 1.4 27/32 ...
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... ESMT FIGURE 21: HOLD TIMING DIAGRAM FIGURE 22: POWER-UP TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L016A Publication Date: Jul. 2008 Revision: 1.4 28/32 ...
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... FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS FIGURE 24: A TEST LOAD EXAMPLE Elite Semiconductor Memory Technology Inc. 0.7VCC AC Measurement Level 0.3VCC Note : Input pulse rise and fall time are <5ns F25L016A Output timing reference level 0.5VCC Publication Date: Jul. 2008 Revision: 1.4 29/32 ...
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... E 0.002 0.006 0.010 E 1 0.067 0.071 0.075 L 0.014 0.016 0.020 e 0.007 0.008 0.010 L 1 θ 0.202 0.206 0.210 F25L016A L L1 DETAIL "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 7.70 7.90 8.10 0.303 0.311 5.18 5.28 5.38 0.204 0.208 0.50 0.65 0.80 0.020 0.026 1 ...
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... Correct Byte Program Time. 2007.03.30 2. Modify ordering information 2008.02.19 Modify the mark of SOIC8 size (page30) 1. Add “All Pb-free products are RoHS-Compliant” in the description of features 2008.07.17 2. Delete bottom block protection table 3. Modify tSE timing 4. Add Revision History F25L016A Description Publication Date: Jul. 2008 Revision: 1.4 31/32 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice F25L016A Publication Date: Jul. 2008 Revision: 1.4 32/32 ...