f25l08pa Elite Semiconductor Memory Technology Inc., f25l08pa Datasheet
f25l08pa
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f25l08pa Summary of contents
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... F25L08PA –100DG 100MHz GENERAL DESCRIPTION The F25L08PA is a 8Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. ...
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... ESMT PIN CONFIGURATIONS 8-PIN SOIC VSS 4 8-PIN PDIP VSS 4 Elite Semiconductor Memory Technology Inc. 8 VDD HOLD 7 SCK VDD HOLD 7 SCK Publication Revision: 1.7 F25L08PA Date: Jul. 2009 2/32 ...
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... The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. X-Decoder Y-Decoder I/O Butters Control Logic Data Latches Serial Interface SCK HOLD F25L08PA Flash and Publication Date: Jul. 2009 Revision: 1.7 3/32 ...
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... ESMT SECTOR STRUCTURE Table 1: F25L08PA Sector Address Table Sector Size Block Sector (Kbytes) 255 4KB 240 4KB 239 4KB 224 4KB 223 4KB 208 4KB 207 4KB 192 4KB 191 4KB 176 4KB 175 4KB 160 4KB 159 4KB 144 4KB ...
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... ESMT Table 1: F25L08PA Sector Address Table - Continued Sector Size Block Sector (Kbytes) 47 4KB 4KB 31 4KB 4KB 15 4KB 4KB STATUS REGISTER The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection ...
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... Auto Address Increment (AAI) The Auto-Address-Increment-Programming-Status bit provides status on whether the device is in AAI Programming mode or Page Program mode. The default at power up is Page Program mode. Table 3: F25L08PA Block Protection Table Status Register Bit BP2 BP1 BP0 Block Range ...
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... ctive Figure 1: HOLD Condition Waveform WRITE PROTECTION F25L08PA provides software Write Protection. The Write-Protect pin ( WP ) enables or disables the lock-down function of the status register. The Block-Protection bits (BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 3 for Block-Protection description ...
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... ESMT INSTRUCTIONS Instructions are used to Read, Write (Erase and Program), and configure the F25L08PA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Auto Address Increment (AAI) Programming, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first ...
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... Non-Applicable Cycles (Cycles are not necessary); cont. = continuous remaining addresses can remaining addresses can and cont. are serial data out; others are serial data in. OUT , OUT1 F25L08PA Publication Date: Jul. 2009 Revision: 1.7 9/32 ...
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... FFFFFH has been read, the next output will be from address location 000000H ADD. ADD. ADD. X MSB MSB F25L08PA - must remain active N+1 N+2 N+3 N ...
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... The Fast Read Dual Output instruction is initiated by executing an 8-bit command, 3BH, followed by address bits [A dummy byte. CE must remain active low for the duration of the Fast Read Dual Output cycle. See Figure 4 for the Fast Read Dual Output sequence. Publication Revision: 1.7 F25L08PA -A ] and Date: Jul. 2009 11/32 ...
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... After the Page Program cycle has finished, the 7 0 Write-Enable-Latch (WEL) bit in the Status Register is cleared to 0. See Figure 7 for the Page Program sequence. F25L08PA Publication Date: Jul. 2009 Revision: 1.7 12/32 ...
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... AAI WORD program operation and return SO pin to output Software Status Register data during AAI WORD programming (refer to Figure 9). Figure 9: Disable SO as Hardware RY/ BY during AAI Programming Publication Revision: 1.7 F25L08PA =0; the second byte with 23 1 The Hardware End of Write BP ...
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... ESMT Figure 10: AAI Word Program Sequence with Hardware End of Write Detection Figure 11: AAI Word Program Sequence with Software End of Write Detection Elite Semiconductor Memory Technology Inc. F25L08PA Publication Date: Jul. 2009 Revision: 1.7 14/32 ...
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... See Figure 14 for the Sector Erase sequence Address bits ADD. MSB MSB HIGH IMPENANCE F25L08PA - Most Significant address) are must be driven high before the IL IH for the completion of the ...
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... Read Status Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE . See Figure 16 for the RDSR instruction sequence. F25L08PA for the completion of the internal self-timed CE Publication Date: Jul. 2009 Revision: 1 ...
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... CE must be driven high before the WRDI instruction is executed MODE3 SCK MODE0 04 SI MSB HIGH IMPENANCE SO instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. F25L08PA Publication Date: Jul. 2009 Revision: 1.7 17/32 ...
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... OTP sector (OTP_lock bit =1). To exit secured OTP mode, user must execute WRDI command. RES can be used to verify the secured OTP status as shown in Table 6. F25L08PA ) prior to the low-to-high transition of the IH STATUS ...
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... In OTP mode, user also can execute RES to confirm the status. Table 6: Electronic Signature Data Mode Electronic Signature Data Normal In secured OTP mode & non lock down (OTP_lock =0) In secured OTP mode & lock down (OTP_lock =1) F25L08PA 13H 33H 73H Publication Date: Jul. 2009 Revision: 1.7 19/32 ...
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... SPI Flash. Byte3, 14H, identifies the device as Figure 22: JEDEC Read-ID Sequence Manufacturer’s ID Elite Semiconductor Memory Technology Inc. F25L08PA. The instruction sequence is shown in Figure 22. The JEDEC Read ID instruction is terminated by a low to high transition any time during data output other instruction, ...
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... ESMT Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L08PA and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H, ...
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... Min Max Unit µA 1 µA 1 µ -0.2 DD Minimum 100 + I DD F25L08PA Value Unit 2.7 ~ 3.6 V 3.0 ~3 ℃ Test Condition CE =0 SO=open =0 SO=open =0 SO=open ...
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... F25L08PA Minimum Unit 10 µs 10 µs Test Condition Maximum OUT Unit Min Max 100 MHz ...
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... Typical values measured at 25°C, 3V. 3. Maximum values measured at 85°C, V Elite Semiconductor Memory Technology Inc. Limit Symbol 2 Typ Max T 90 200 1 100 100,000 - 20 - (min) DD F25L08PA Unit Cycles Years Publication Date: Jul. 2009 Revision: 1.7 24/32 ...
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... ESMT Figure 24: Serial Input Timing Diagram Figure 25: Serial Output Timing Diagram Elite Semiconductor Memory Technology Inc. F25L08PA Publication Date: Jul. 2009 Revision: 1.7 25/32 ...
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... V CC (max) Program, Erase and Write command is ignored CE must track V CC (min) T Reset VSL State PUW Threshold WI Symbol Min. T 200 VSL T PUW F25L08PA Read command Device is fully is allowed accessible Time Max. Unit Publication Date: Jul. 2009 Revision: 1.7 26/32 ...
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... Figure 28: AC Input/Output Reference Waveforms Figure 29: A Teat Load Example Elite Semiconductor Memory Technology Inc. Input timing reference level 0.7VCC Measurement 0.3VCC Note : Input pulse rise and fall time are <5ns F25L08PA Output timing reference level AC 0.5VCC Level Publication Revision: 1.7 Date: Jul. 2009 ...
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... D 0.004 0.006 0.010 E 0.049 0.057 0.061 L 0.013 0.016 0.020 e 0.0075 0.008 0.010 L 1 θ 0.228 0.236 0.244 F25L08PA GAUGE PLANE L DETAIL "X" "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 4.80 4.90 5.00 0.189 0.193 3.80 3.90 4.00 0.150 0.154 0.40 0.66 0.86 ...
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... E 0.002 0.006 0.010 E 1 0.067 0.071 0.075 L 0.014 0.016 0.020 e 0.007 0.008 0.010 L 1 θ 0.202 0.206 0.210 F25L08PA L L1 DETAIL "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 7.70 7.90 8.10 0.303 0.311 5.18 5.28 5.38 0.204 0.208 0.50 0.65 0.80 0.020 0.026 1 ...
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... Min Norm Max 5.00 0.38 3.18 3.30 3.43 9.02 9.27 10.16 7.62 BSC. 6.22 6.35 6.48 9.02 9.27 10.16 2.54 TYP. 8.51 9.02 9.53 0.46 TYP. 1.52 TYP F25L08PA 0 Dimension in inch Min Norm Max 0.21 0.015 0.125 0.130 0.135 0.355 0.365 0.400 0.300 BSC. 0.245 0.250 0.255 0.115 0.130 0.150 0.100 TYP. 0.335 0.355 0.375 0.018 TYP. 0.060 TYP ...
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... Modify tSE timing 1. Modify the error of Device ID 2008.11.19 2. Delete T and T BP1 1.Modify headline 2009.05.11 2.Delete the rating of Temperature Under Bias 2009.06.04 Add 8 lead SOIC (150mil) package 2009.07.20 Modify the description of OTP mode Description (page1,12,23) BP2 Publication Revision: 1.7 F25L08PA Date: Jul. 2009 31/32 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice F25L08PA Publication Date: Jul. 2009 Revision: 1.7 32/32 ...