f25l08pa Elite Semiconductor Memory Technology Inc., f25l08pa Datasheet - Page 8

• Manufacturer Part Number: f25l08pa
• Description: 3v Only 8 Mbit Serial Flash Memory With Dual
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Instructions are used to Read, Write (Erase and Program), and
configure the F25L08PA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Auto Address Increment (AAI)
Programming, Write Status Register, Sector Erase, Block Erase,
or Chip Erase instructions, the Write Enable (WREN) instruction
must be executed first. The complete list of the instructions is
provided in Table 5. All instructions are synchronized off a high to
low transition of CE . Inputs will be accepted on the rising edge
of SCK starting with the most significant bit. CE must be driven
Read
Fast Read
Fast Read Dual
Output
Sector Erase
Block Erase
Chip Erase
Page Program (PP)
Auto Address Increment
word programming
Read Status Register
(RDSR)
Enable Write Status
Register (EWSR)
Write Status Register
(WRSR)
Write Enable (WREN)
Write Disable (WRDI)/
Exit secured OTP mode
Enter secured OTP mode
(ENSO)
Read Electronic
Signature (RES)
RES in secured OTP
mode & not lock down
RES in secured OTP
mode & lock down
Jedec Read ID
(JEDEC-ID)
Read ID (RDID)
Enable SO to output
RY/
(EBSY)
Disable SO to output
RY/
(DBSY)
Elite Semiconductor Memory Technology Inc.
INSTRUCTIONS
12,13
Operation
Status during AAI
Status during AAI
6
7
4,
9
4
(64K Byte)
(4K Byte)
11
8
7
5
(AAI)
10
100
33
50
Max.
Freq
MHz
MHz
MHz
60H /
ADH
ABH
ABH
ABH
0BH
D8H
C7H
B1H
9FH
03H
20H
02H
05H
50H
01H
06H
04H
90H
70H
80H
S
IN
3BH
1
S
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z
Hi-Z A
Hi-Z A
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table 5: Device Operation Instructions
OUT
23
23
23
23
23
23
00H
S
D
X
X
X
X
X
-A
-A
-A
-A
-
-A
-A
-
-
-
-
-
-
A
IN
IN
23
16
16
16
16
16
16
2
-A
16
S
D
8CH
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z
13H
33H
73H
Hi-Z
OUT
OUT
-
-
-
-
-
-
-
00H
15
15
15
15
15
15
S
X
-
-
-
-
-
-
-
-
-
-
-
-
IN
-A
-A
-A
-A
-A
-A
A
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read ID, Read Status Register, Read Electronic Signature
instructions). Any low to high transition on CE , before receiving
the last bit of an instruction bus cycle, will terminate the
instruction in progress and return the device to the standby
mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
15
8
8
8
8
8
8
3
-A
S
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
20H
Hi-Z
8
OUT
-
-
-
-
-
-
-
-
-
-
-
-
Bus Cycle
00H
01H
S
7
7
7
7
7
7
-.
-.
-.
-.
X
-A
-A
-A
-A
-
-A
-A
-
-
-
-
-
-
-
IN
A
0
0
0
0
0
0
7
4
-A
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
14H
Hi-Z
Hi-Z
0
OUT
-
-
-
-
-
-
-
-
-
-
-
-
1~3
D
D
S
X
X
X
X
-
-
-
-
-
-
-
-
IN0
IN0
-
-
-
-
-
-
-
IN
Publication
Revision: 1.7
5
X
D
S
8CH
Hi-Z
Hi-Z
13H
OUT0
OUT
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D
D
S
F25L08PA
X
X
X
X
-
-
-
IN1
IN1
-
-
-
-
-
-
-
-
-
-
-
-
IN
Date: Jul. 2009
D
OUT0~1
6
D
D
S
8CH
Hi-Z
Hi-Z
13H
OUT1
OUT0
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Up to
bytes
8/32
256
S
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IN
cont.
N
cont.
cont.
S
Hi-Z
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-