f25l04ua Elite Semiconductor Memory Technology Inc., f25l04ua Datasheet
f25l04ua
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f25l04ua Summary of contents
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... SOIC F25L04UA -100PG 100MHz 8 lead SOIC GENERAL DESCRIPTION The F25L04UA is a 4Megabit, 3V only CMOS Serial Flash memory device. ESMT’s memory devices reliably store memory data even after 100,000 program and erase cycles. The F25L04UA features a sector erase architecture. The device memory array is divided into one 8K bytes, two 4K bytes, one 16K bytes, one 32K bytes, and seven 64K bytes ...
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... Data is shifted out on the falling edge of SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporaiily stop serial communication with SPI flash memory without resetting the device. To provide power. F25L04UA Publication Date: Jan. 2009 Revision: 1.2 2/25 ...
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... ESMT SECTOR STRUCTURE Table1 : F25L04UA Sector Address Table Sector Size Symbol (Kbytes) 11 8KB 10 4KB 9 4KB 8 16KB 7 32KB 6 64KB 5 64KB 4 64KB 3 64KB 2 64KB 1 64KB 0 64KB Table2 : F25L04UA Block Protection Table Protection Level 0 1(1/8 memory array) 2(1/4 memory array) 3(all memory array) Block Protection (BP1, BP0) ...
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... ESMT FUNTIONAL BLOCK DIAGRAM Address Buffers and Latches CE Elite Semiconductor Memory Technology Inc. SuperFlash X-Decoder Memory Y-Decoder I/O Butters Control Logic Data Latches Serial Interface SCK SO WP HOLD SI F25L04UA and Publication Date: Jan. 2009 Revision: 1.2 4/25 ...
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... ctive Figure 3 : HOLD CONDITION WAVEFORM Write Protection F25L04UA provides software Write protection. The Write Protect pin ( WP ) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 2 for Block-Protection description ...
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... Block-Erase instruction completion • Chip-Erase instruction completion Elite Semiconductor Memory Technology Inc. the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Function F25L04UA Default at Read/Write Power- ...
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... ESMT Instructions Instructions are used to Read, Write (Erase and Program), and configure the F25L04UA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, instructions, the Write-Enable (WREN) instruction must be executed first ...
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... The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A low for the duration of the Read cycle. See Figure 4 for the Read sequence ADD. ADD. ADD. MSB N D OUT MSB F25L04UA - must remain active N+1 N+2 N+3 N ...
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... Mbit density, once the data from address location 07FFFFH has been read, the next output will be from address location 000000H ADD. ADD. ADD. X MSB MSB F25L04UA is reached, the address N+1 N+2 N+3 N ...
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... Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 6 for the Byte-Program sequence ADD. ADD. MSB HIGH IMPENANCE F25L04UA -A ]. Following the address, the data ADD. D ...
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... TBP 101112 1314 Last Data Byte 04 Write Disable (WRDI) Instruction to terminate AAI Operation F25L04UA TBP 1213 Data Byte 1213 Read Status Register(RDSR) Instruction to verify end of ...
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... TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 8 for the Sector-Erase sequence Address bits DD. ADD. MSB HIGH IMPENANCE F25L04UA ] (A = Most Significant address) are used to determine remaining address bits can be VIL DD Publication Date: Jan ...
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... Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE See Figure 10 for the RDSR instruction sequence Bit7 MSB F25L04UA for the completion of the internal self-timed Chip-Erase CE 60 remain low until the status ...
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... EWSR instruction is executed. Elite Semiconductor Memory Technology Inc MODE3 SCK MODE0 06 SI MSB HIGH IMPENANCE MODE3 SCK MODE0 04 SI MSB HIGH IMPENANCE SO F25L04UA Publication Date: Jan. 2009 Revision: 1.2 14/25 ...
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... WRSR instruction is executed. See Figure 13 for EWSR and WRSR instruction sequences 1011 12 13 1415 50 MSB HIGH IMPENANCE F25L04UA ) prior to the low-to-high transition of the CE pin IH STATUS REGISTER Publication Date: Jan ...
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... HIGH IMPENANCE SO Jedec-Read-ID DATA Manufacture’s ID Memory Type Byte1 Byte2 8CH 8CH Elite Semiconductor Memory Technology Inc. 1011 1920 2122 23 24 2526 27 282930 MSB MSB Device ID Memory Capacity Byte3 8CH F25L04UA 8C 8C Publication Date: Jan. 2009 Revision: 1.2 16/25 ...
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... CLK 0~70 Limits Min Max Units µA 1 µA 1 µA 0 0 Parameter Description F25L04UA Unit V °C Test Conditions CE =0.1 V /0.9 V @33 MHz, SO=open VIN =GND Max =GND ...
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... F25L04UA Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 Units Max Min Max 75 100 MHz 100 ...
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... Tested, Excludes external system level over head. 2.Typical values measured at 25°C, 3V. 3.Maximum values measured at 85°C, V Elite Semiconductor Memory Technology Inc. Limits Symbol Typ.(2) Max.(3) 0 4.5 13.5 100,000 (min). DD F25L04UA Unit 15 sec 50 sec 300 us sec - Cycles Publication Date: Jan. 2009 Revision: 1.2 19/25 ...
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... ESMT FIGURE 15: SERIAL INPUT TIMING DIAGRAM FIGURE 16: SERIAL OUTPUT TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L04UA Publication Date: Jan. 2009 Revision: 1.2 20/25 ...
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... ESMT CE# SCK SO SI HOLD# FIGURE 17: HOLD TIMING DIAGRAM FIGURE 18: POWER-UP TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L04UA Publication Date: Jan. 2009 Revision: 1.2 21/25 ...
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... FIGURE 19: AC INPUT/OUTPUT REFERENCE WAVEFORMS FIGURE 20: A TEST LOAD EXAMPLE Elite Semiconductor Memory Technology Inc. 0.7VCC AC Measurement Level 0.3VCC Note : Input pulse rise and fall time are <5ns F25L04UA Output timing reference level 0.5VCC Publication Date: Jan. 2009 Revision: 1.2 22/25 ...
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... D 0.004 0.006 0.010 E 0.049 0.057 0.061 L 0.013 0.016 0.020 e 0.0075 0.008 0.010 L 1 θ 0.228 0.236 0.244 F25L04UA GAUGE PLANE L DETAIL "X" "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 4.80 4.90 5.00 0.189 0.193 3.80 3.90 4.00 0.150 0.154 0.40 0.66 0.86 ...
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... Correct the size of "L" in the packaging diagram of SOIC 150 mil 2. Add operating range table 3. Delete the rating of Temperature Under Bias 2008.01.13 4. Add the symbol for erase and byte programming time 5. Correct typo error 6. Modify headline 7. Add Revision History 8. Correct part no. F25L04UA Description Publication Date: Jan. 2009 Revision: 1.2 24/25 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice F25L04UA Publication Date: Jan. 2009 Revision: 1.2 25/25 ...