f25l04ua Elite Semiconductor Memory Technology Inc., f25l04ua Datasheet - Page 11

• Manufacturer Part Number: f25l04ua
• Description: Only Mbit Serial Flash Memory
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Auto Address Increment (AAI) Program
The AAI program instruction allows multiple bytes of data to be
programmed without re-issuing the next sequential address
location. This feature decreases total programming time when
the entire memory array is to be programmed. An AAI program
instruction pointing to a protected memory area will be ignored.
The selected address range must be in the erased state (FFH)
when initiating an AAI program instruction.
Prior to any write operation, the Write-Enable (WREN) instruction
must be executed. The AAI program instruction is initiated by
executing an 8-bit command, AFH, followed by address bits
[A
from MSB (bit 7) to LSB (bit 0). CE must be driven high before
the AAI program instruction is executed. The user must poll the
Figure 7 : AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE
Elite Semiconductor Memory Technology Inc.
23
-A
0
]. Following the addresses, the data is input sequentially
SCK
SCK
SO
CE
CE
SI
SI
MODE0
MODE3
0 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8 9
AF
AF
A[23,16]
Last Data Byte
101112 1314 15
15 16
A[15,8]
23 24
TBP
A[7,0]
31 32
0 1 2 3 4 5 6 7
Write Disable (WRDI)
Instruction to terminate
AAI Operation
333435 36 373839
Data Byte 1
04
BUSY bit in the software status register or wait TBP for the
completion of each internal self-timed Byte-Program cycle. Once
the device completes programming byte, the next sequential
address may be program, enter the 8-bit command, AFH,
followed by the data to be programmed. When the last desired
byte had been programmed, execute the Write-Disable (WRDI)
instruction, 04H, to terminate AAI. After execution of the WRDI
command, the user must poll the Status register to ensure the
device completes programming. See Figure 7 for AAI
programming sequence.
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the device will
exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0).
TBP
0 1 2 3 4 5 6 7 8 9 10 11 1213 14 15
0 1 2 3 4 5 6 7 8 9 10 11 1213 14 15
Read Status Register(RDSR)
Instruction to verify end of
AAI Operation
05
AF
Publication Date: Jan. 2009
Revision:
Data Byte 2
D
F25L04UA
OUT
1.2
TBP
0 1
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