f25l008a Elite Semiconductor Memory Technology Inc., f25l008a Datasheet
f25l008a
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f25l008a Summary of contents
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... F25L008A –100DG 100MHz 8 lead PDIP GENERAL DESCRIPTION The F25L008A is a 8Megablt, 3V only CMOS Serial Flash memory device organized as 1M bytes of 8 bits. This device is packaged in 8-lead SOIC 200mil. ESMT’s memory devices reliably store memory data even after 100,000 program and erase cycles ...
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... ESMT PIN CONFIGURATIONS 8-PIN SOIC VSS 4 8-PIN PDIP VSS 4 Elite Semiconductor Memory Technology Inc. 8 VDD HOLD 7 SCK VDD HOLD 7 SCK Publication Date: Jul. 2008 Revision: F25L008A 1.6 2/32 ...
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... Data is shifted out on the falling edge of SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. F25L008A Publication Date: Jul. 2008 Revision: 1.6 3/32 ...
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... ESMT SECTOR STRUCTURE Table1 : F25L008A Sector Address Table Sector Size Sector Block (Kbytes) 255 4KB 240 4KB 239 4KB 224 4KB 223 4KB 208 4KB 207 4KB 192 4KB 191 4KB 176 4KB 175 4KB 160 4KB 159 4KB 144 4KB ...
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... Table2 : F25L008A Block Protection Table Protection Level BP2 0 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks All Blocks Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Program or Erase) operations ...
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... ESMT FUNTIONAL BLOCK DIAGRAM Address Buffers and Latches CE Elite Semiconductor Memory Technology Inc. X-Decoder Y-Decoder I/O Butters Control Logic Data Latches Serial Interface SCK HOLD F25L008A Flash and Publication Date: Jul. 2008 Revision: 1.6 6/32 ...
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... ctive Figure 1 : HOLD CONDITION WAVEFORM Write Protection F25L008A provides software Write protection. The Write Protect pin ( WP ) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description ...
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... Table 4 describes the function of each bit in the software status register. Function accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: F25L008A Default at Read/Write Power- ...
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... ESMT Instructions Instructions are used to Read, Write (Erase and Program), and configure the F25L008A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5 ...
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... The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A low for the duration of the Read cycle. See Figure 2 for the Read sequence ADD. ADD. ADD. MSB N D OUT MSB F25L008A - must remain active N+1 N+2 N+3 N ...
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... FFFFFH has been read, the next output will be from address location 000000H ADD. ADD. ADD. X MSB MSB F25L008A is reached, the address N+1 N+2 N+3 N ...
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... Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 4 for the Byte-Program sequence ADD. ADD. MSB HIGH IMPENANCE F25L008A -A ]. Following the address, the data ADD. D ...
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... DURING AAI PROGRAMMING Elite Semiconductor Memory Technology Inc Following the addresses, two bytes of data is input sequentially FIGURE 9 : DISABLE SO AS HARDWARE DURING AAI PROGRAMMING F25L008A . Refer to End-of-Write with A =1. CE must be driven The hardware end of write detection BP. ...
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... ESMT FIGURE 10 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETETION FIGURE 11 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETETION Elite Semiconductor Memory Technology Inc. F25L008A Publication Date: Jul. 2008 Revision: 1.6 14/32 ...
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... VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See Figure 5 for the Block-Erase sequence. Publication Date: Jul. 2008 Revision: F25L008A = Most Significant address) ), remaining X 1.6 15/32 ...
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... Sector-Erase cycle. See Figure 6 for the Sector-Erase sequence Address bits ADD. MSB MSB HIGH IMPENANCE F25L008A ] (A = Most Significant address) are used to determine remaining address bits can be VIL ADD. ADD. Publication Date: Jul. 2008 Revision: 1 ...
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... Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE See Figure 8 for the RDSR instruction sequence Bit7 MSB F25L008A for the completion of the internal self-timed remain low until the status ...
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... CE must be driven high before the WRDI instruction is executed. Figure 10 : WRITE DISABLE (WRDI) SEQUENCE Elite Semiconductor Memory Technology Inc MODE3 SCK MODE0 06 SI MSB HIGH IMPENANCE MODE3 SCK MODE0 04 SI MSB HIGH IMPENANCE SO F25L008A Publication Date: Jul. 2008 Revision: 1.6 18/32 ...
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... BP0 ;BP1 and BP2 bits at the same time. See Table 3 for a summary description of WP and BPL functions 1011 12 13 1415 MSB HIGH IMPENANCE F25L008A ) prior to the low-to-high transition of the IH STATUS REGISTER Publication Date: Jul ...
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... µA V OUT 0 =100 µ -0.2 0 =-100 µ Parameter Description F25L008A Test Conditions /0.9 V @33 MHz, SO=open VIN Max =GND Max Min DD =V Max ...
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... Erase, Program or WRSR cycle is in progress is no decoded, and has no effect on the cycle in progress. CE MODE3 0 1 SCK MODE1 SI MSB HIGH IMPENANCE SO Figure 12 : Read-Electronic-Signature (RES) Elite Semiconductor Memory Technology Inc Bit7 MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Status Register Out Publication Date: Jul. 2008 Revision: 1.6 F25L008A 21/32 ...
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... After that, a 16-bit device ID is shifted out on the SO pin. Byte1, BFH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 14H, identifies the device as F25L008A. The instruction sequence is shown in Figure13. The JEDEC Read ID instruction is terminated by a low to high transition any time during data output other command is ...
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... ESMT Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L008A and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Following the Read-ID instruction, the manufacturer’ ...
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... F25L008A Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 Max Units 100 MHz ...
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... Tested, Excludes external system level over head. 2.Typical values measured at 25°C, 3V. 3.Maximum values measured at 85°C, 2.7V. Elite Semiconductor Memory Technology Inc. Limits Unit Typ.(2) Max.(3) 90 200 100 100,000 - Cycles 20 - Years F25L008A Publication Date: Jul. 2008 Revision: 1.6 25/32 ...
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... ESMT FIGURE 15: SERIAL INPUT TIMING DIAGRAM FIGURE 16: SERIAL OUTPUT TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L008A Publication Date: Jul. 2008 Revision: 1.6 26/32 ...
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... ESMT FIGURE 17: HOLD TIMING DIAGRAM FIGURE 18: POWER-UP TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L008A Publication Date: Jul. 2008 Revision: 1.6 27/32 ...
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... FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS FIGURE 20: A TEST LOAD EXAMPLE Elite Semiconductor Memory Technology Inc. 0.7VCC AC Measurement Level 0.3VCC Note : Input pulse rise and fall time are <5ns F25L008A Output timing reference level 0.5VCC Publication Date: Jul. 2008 Revision: 1.6 28/32 ...
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... E 0.002 0.006 0.010 E 1 0.067 0.071 0.075 L 0.014 0.016 0.020 e 0.007 0.008 0.010 L 1 θ 0.202 0.206 0.210 F25L008A L L1 DETAIL "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 7.70 7.90 8.10 0.303 0.311 5.18 5.28 5.38 0.204 0.208 0.50 0.65 0.80 0.020 0.026 1 ...
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... Min Norm Max 5.00 0.38 3.18 3.30 3.43 9.02 9.27 10.16 7.62 BSC. 6.22 6.35 6.48 9.02 9.27 10.16 2.54 TYP. 8.51 9.02 9.53 0.46 TYP. 1.52 TYP F25L008A 0 Dimension in inch Min Norm Max 0.21 0.015 0.125 0.130 0.135 0.355 0.365 0.400 0.300 BSC. 0.245 0.250 0.255 0.115 0.130 0.150 0.100 TYP. 0.335 0.355 0.375 0.018 TYP. 0.060 TYP ...
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... AAI function use 1 word Din (Page8) 1. Correct Byte Program Time. 2007.04.04 2. Modify ordering information. 1. Add “All Pb-free products are ROHS-Compliant” in the description of features 2008.07.17 2. Delete bottom block protection table 3. Modify tSE timing 4. Add Revision History F25L008A Description Publication Date: Jul. 2008 Revision: 1.6 31/32 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice F25L008A Publication Date: Jul. 2008 Revision: 1.6 32/32 ...