f25l008a Elite Semiconductor Memory Technology Inc., f25l008a Datasheet - Page 13

• Manufacturer Part Number: f25l008a
• Description: 3v Only Serial Flash Memory
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location.
This feature decreases total programming time when the multiple bytes or entire memory array is to be programmed. An AAI program
instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when
initiating an AAI program instruction. While within AAI WORD programming sequence, the only valid instructions are AAI WORD
program operation, RDSR, WRDI. Users have three options to determine the completion of each AAI WORD program cycle: hardware
detection by reading the SO; software detection by polling the BUSY in the software status register or wait T
Detection section for details.
Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI WORD program instruction is initiated by
executing an 8-bit command, ADH, followed by address bits [A
The data is input sequentially from MSB (bit 7) to LSB (bit 0). The first byte of data(DO) will be programmed into the initial address
[A
high before the AAI WORD program instruction is executed. The user must check the BUSY status before entering the next valid
command. Once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. When
the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the
WRDI instruction, to terminate AAI. User must check busy status after WRDI to determine if the device is ready for any command.
Please refer to Figures 9 and Figures 10.
There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI
operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI bit (AAI=0).
End of Write Detection
There are three methods to determine completion of a program cycle during AAI WORD programming: hardware detection by reading
the SO, software detection by polling the BUSY bit in the Software Status Register or wait T
method is described in the section below.
Hardware End of Write Detection
The hardware end of write detection method eliminates the overhead of polling the BUSY bit in the software status register during an AAI
Word PROGRAM OPERATION. The 8bit command, 70H, configures the SO to indicate Flash Busy status during AAI WORD
programming (refer to figure7). The 8bit command, 70H, must be executed prior to executing an AAI WORD program instruction. Once
an internal programming operation begins, asserting CE will immediately drive the status of the internal flash status on the SO pin. A “0”
Indicates the device is busy ; a “1” Indicates the device is ready for the next instruction. De-asserting CE will return the SO pin to
tri-state. The 8bit command, 80H,disables the SO pin to output busy status during AAI WORD program operation and return SO pin to
output software register data during AAI WORD programming (refer to figure8).
FIGURE 8 : ENABLE SO AS HARDWARE
Elite Semiconductor Memory Technology Inc.
Auto Address Increment (AAI) WORD Program
23
-A
1
] with A
DURING AAI PROGRAMMING
0
=0; The second byte of data(D1) will be programmed into the initial address [A
RY
/
BY
23
-A
FIGURE 9 : DISABLE SO AS HARDWARE
0
]. Following the addresses, two bytes of data is input sequentially.
DURING AAI PROGRAMMING
BP.
The hardware end of write detection
Publication Date: Jul. 2008
Revision:
23
-A
1
] with A
1.6
BP
0
F25L008A
=1. CE must be driven
RY
. Refer to End-of-Write
/
BY
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