f25l08pa Elite Semiconductor Memory Technology Inc., f25l08pa Datasheet - Page 6

• Manufacturer Part Number: f25l08pa
• Description: 3v Only 8 Mbit Serial Flash Memory With Dual
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
• Power-up
• Write Disable (WRDI) instruction completion
• Page Program instruction completion
• Auto Address Increment (AAI) Programming is completed and
• Sector Erase instruction completion
• Block Erase instruction completion
• Chip Erase instruction completion
• Write Status Register instructions
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
BP2, BP1, BP0 bits as long as WP is high or the Block-
Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to1.
Elite Semiconductor Memory Technology Inc.
reached its highest unprotected memory address
Protection Level
Upper 1/16
All Blocks
All Blocks
All Blocks
Upper 1/8
Upper 1/4
Upper 1/2
0
Table 3: F25L08PA Block Protection Table
BP2
0
0
0
0
1
1
1
1
Status Register Bit
BP1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
BUSY
The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
Auto Address Increment (AAI)
The Auto-Address-Increment-Programming-Status bit provides
status on whether the device is in AAI Programming mode or
Page Program mode. The default at power up is Page Program
mode.
Block Protection Lock-Down (BPL)
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
WP pin driven low (V
WP pin is driven high (V
Block Range
Block 12~15
Block 14~15
Block 0~15
Block 8~15
Block 0~15
Block 0~15
Block 15
None
Protected Memory Area
IH
Publication
IL
Revision: 1.7
), enables the Block-Protection-
), the BPL bit has no effect and its
C0000H – FFFFFH
E0000H – FFFFFH
00000H – FFFFFH
F0000H – FFFFFH
80000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
Address Range
None
F25L08PA
Date: Jul. 2009
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