f25l016a Elite Semiconductor Memory Technology Inc., f25l016a Datasheet - Page 20

• Manufacturer Part Number: f25l016a
• Description: 3v Only Serial Flash Memory
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the
Write-Status-Register (WRSR) instruction and opens the status
register
instruction does not have any effect and will be wasted, if it is not
followed immediately by the Write-Status-Register (WRSR)
instruction. CE must be driven low before the EWSR instruction
is entered and must be driven high before the EWSR instruction
is executed.
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the
BP2, BP1, BP0, and BPL bits of the status register. CE must be
driven low before the command sequence of the WRSR
instruction is entered and driven high before the WRSR
instruction is executed. See Figure 15 for EWSR or WREN and
WRSR instruction sequences.
Executing the Write-Status-Register instruction will be ignored
when WP is low and BPL bit is set to “1”. When the WP is
low, the BPL bit can only be set from “0” to “1” to lockdown the
status register, but cannot be reset from “1” to “0”.
Figure 15 : ENABLE-WRITE-STATUS-REGISTER (EWSR) or WRITE-ENABLE(WREN) and WRITE-STATUS-REGISTER (WRSR)
Elite Semiconductor Memory Technology Inc.
for
SCK
SO
CE
SI
alteration.
MODE0
MODE3
MSB
The
0 1 2 3 4 5 6 7
50 or 06
Enable-Write-Status-Register
HIGH IMPENANCE
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, BP1,and BP2 bits in the status
register can all be changed. As long as BPL bit is set to 0 or WP
pin is driven high (V
register can all be altered by the WRSR instruction. In this case,
a single WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0 ;BP1 and BP2 bits
at the same time. See Table 3 for a summary description of WP
and BPL functions.
CE pin at the end of the WRSR instruction, the bits in the status
0 1 2 3 4 5 6 7 8 9 1011 12 13 1415
MSB
01
IH
7 6 5 4 3 2 1 0
) prior to the low-to-high transition of the
REGISTER IN
Publication Date: Jul. 2008
Revision:
STATUS
F25L016A
1.4
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