F25L004A-50PAIG ELITE SEMICONDUCTOR, F25L004A-50PAIG Datasheet - Page 7

• Manufacturer Part Number: F25L004A-50PAIG
• Description: IC, FLASH, 4MBIT, 50MHZ, SOIC-8
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of F25L004A-50PAIG

• Memory Type: Flash
• Memory Size: 4Mbit
• Memory Configuration: 512 X 8
• Ic Interface Type: Serial, SPI
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
Hold Operation
SPI flash memory without resetting the clocking sequence. To
activate the HOLD mode, CE must be in active low state. The
with the falling edge of the HOLD signal. The HOLD mode ends
when the HOLD signal’s rising edge coincides with the SCK
active low state.
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD signal does not
Figure 1 : HOLD CONDITION WAVEFORM
Write Protection
F25L004A provides software Write protection.
The Write Protect pin ( WP ) enables or disables the lockdown
function of the status register. The Block-Protection bits (BP1,
BP0, and BPL) in the status register provide Write protection to
the memory array and the status register. See Table 5 for
Block-Protection description.
Write Protect Pin ( WP )
The Write Protect ( WP ) pin enables the lock-down function of
the BPL bit (bit 7) in the status register. When WP is driven low,
the execution of the Write-Status-Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 3). When WP
is high, the lock-down function of the BPL bit is disabled.
Elite Semiconductor Memory Technology Inc.
HOLD pin is used to pause a serial sequence underway with the
HOLD mode begins when the SCK active low state coincides
HO L D
S CK
A ctive
Ho ld
coincide with the SCK active low state, then the device exits in
Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be V
If CE is driven active high during a Hold condition, it resets the
internal logic of the device. As long as HOLD signal is low, the
memory
communication with the device, HOLD must be driven active
high, and CE must be driven active low. See Figure 18 for Hold
timing.
TABLE3: CONDITIONS TO EXECUTE
WRITE-STATUS- REGISTER (WRSR)
INSTRUCTION
WP
H
L
L
A ctive
BPL
Operation Temperature condition -40
X
1
0
remains
Execute WRSR Instruction
Ho ld
in
Publication Date: Oct. 2007
Not Allowed
the
Allowed
Allowed
Revision:
Hold
IL
or V
IH
condition.
.
A ctive
F25L004A
1.1
To
7/32
°
C
~85
resume
°
C