LPC1226FBD48/301 NXP Semiconductors, LPC1226FBD48/301 Datasheet - Page 16
![MCU, 96K FLASH, CORTEX-M0, 48LQFP](/photos/19/0/190032/ge48lqfp05-40_sml.jpg)
LPC1226FBD48/301
Manufacturer Part Number
LPC1226FBD48/301
Description
MCU, 96K FLASH, CORTEX-M0, 48LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1224FBD48201.pdf
(60 pages)
Specifications of LPC1226FBD48/301
Rohs Compliant
YES
Featured Product
LPC122x Cortex-M0 Microcontrollers
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
45MHz
Connectivity
I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
39
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
LPC1200
No. Of I/o's
39
Ram Memory Size
8KB
Cpu Speed
30MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5161
LPC1226FBD48/301
LPC1226FBD48/301
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1226FBD48/301
Manufacturer:
ROHM
Quantity:
12 000
Company:
Part Number:
LPC1226FBD48/301,1
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
7. Functional description
LPC122X
Objective data sheet
7.1.1 System tick timer
7.1 ARM Cortex-M0 processor
7.2 On-chip flash program memory
7.3 On-chip SRAM
7.4 Memory map
Table 4.
[1]
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
The ARM Cortex-M0 includes a System Tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval.
The LPC122x contain up to 128 kB of on-chip flash memory.
The LPC122x contain a total of up to 8 kB on-chip static RAM memory.
The LPC122x incorporates several distinct memory regions, shown in the following
figures.
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128
peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
Peripheral
SWD
Reset
Clockout pin
After reset, the SWD functions are selected by default on pins PIO0_26 and PIO0_25.
Figure 4
Pin multiplexing
All information provided in this document is subject to legal disclaimers.
shows the overall map of the entire address space from the user
Rev. 1.2 — 29 March 2011
Function
SWCLK
SWDIO
RESET
CLKOUT
[1]
[1]
Type
I
I/O
I
O
32-bit ARM Cortex-M0 microcontroller
Available on ports:
PIO0_18
PIO0_25
PIO0_13
PIO0_12
PIO0_26
PIO1_2
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LPC122x
© NXP B.V. 2011. All rights reserved.
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