LPC2212FBD144 NXP Semiconductors, LPC2212FBD144 Datasheet - Page 20

• Manufacturer Part Number: LPC2212FBD144
• Description: 16/32BIT MCU ARM7, 128K FLASH, 144LQFP
• Manufacturer: NXP Semiconductors

Specifications of LPC2212FBD144

• No. Of I/o's: 112
• Ram Memory Size: 16KB
• Cpu Speed: 60MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 6
• Digital Ic Case: RoHS Compliant
• Core Size: 32bit
• Program Memory Size: 128KB
• Oscillator Type: External Only
• Controller Family/series: LPC22xx
• Rohs Compliant: Yes

NXP Semiconductors
LPC2212_2214_4
Product data sheet
6.14.2 Features available in LPC2212/2214/01 only
6.15.1 Features
6.16.1 Features
6.15 Watchdog timer
6.16 Real-time clock
The LPC2212/2214/01 can count external events on one of the capture inputs if the
external pulse lasts at least one half of the period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs, or used as external
interrupts.
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the Watchdog within a predetermined
amount of time.
The RTC is designed to provide a set of counters to measure time when normal or idle
operating mode is selected. The RTC has been designed to use little power, making it
suitable for battery powered systems where the CPU is not running continuously (Idle
mode).
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– Toggle on match.
– Do nothing on match.
Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied
clock.
When counting cycles of an externally supplied clock, only one of the timer’s capture
inputs can be selected as the timer’s clock. The rate of such a clock is limited to
PCLK / 4. Duration of high/low levels on the selected CAP input cannot be shorter
than 1 / (2PCLK).
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (T
T
Measures the passage of time to maintain a calendar and clock.
Ultra low power design to support battery powered systems.
cy(PCLK)
4.
Rev. 04 — 3 January 2008
cy(PCLK)
256
4) to (T
16/32-bit ARM microcontrollers
cy(PCLK)
LPC2212/2214
2
32
© NXP B.V. 2008. All rights reserved.
4) in multiples of
20 of 45