UPD78F0886GA(A)-GAM-AX NEC, UPD78F0886GA(A)-GAM-AX Datasheet - Page 15

• Manufacturer Part Number: UPD78F0886GA(A)-GAM-AX
• Description: 8BIT MCU, 60K FLASH, 3KB RAM, CAN
• Manufacturer: NEC

Specifications of UPD78F0886GA(A)-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm Channels: 6
• Digital Ic Case Style: LQFP
• Core Size: 8bit
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(1) Interrupt enable flag (IE)
(2) Zero flag (Z)
(3) Register bank select flags (RBS0 and RBS1)
(4) Auxiliary carry flag (AC)
(5) In-service priority flag (ISP)
(6) Carry flag (CY)
This flag controls the interrupt request acknowledgement operations of the CPU.
When IE = 0, the IE flag is set to interrupt disable (DI), and interrupts other than non-maskable interrupts
are all disabled.
When IE = 1, the IE flag is set to interrupt enable (EI), and interrupt request acknowledgement is controlled
by an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
This flag is reset (0) upon DI instruction execution or interrupt request acknowledgment and is set (1) upon
execution of the EI instruction.
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
These are 2-bit flags used to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SBL RBn instruction
execution is stored.
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, vectored
interrupt requests specified as low priority by the priority specification flag register (PR) are disabled for
acknowledgment. Actual acknowledgment for interrupt requests is controlled by the state of the interrupt
enable flag (IE).
This flag stores an overflow or underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
User's Manual U12326EJ4V0UM
CHAPTER 2 REGISTERS
15