AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet - Page 31

• Manufacturer Part Number: AU80610004671AAS LBMH
• Description: MPU, ATOM PROCESSOR, D410, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D400r

Specifications of AU80610004671AAS LBMH

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.5.2
1.5.3
Datasheet
DID - Device Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
PCICMD - PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Since CPU Uncore Device #0 does not physically reside on PCI_A, many of the bits are
not implemented.
15:10
15:0
Bit
Bit
9
8
Access
Access
RW
RO
RO
RO
Default
Default
Value
A000h
Value
00h
0b
0b
RST/
PWR
Core
Core
Core
0/0/0/PCI
2-3h
A000h
16 bits
0/0/0/PCI
4-5h
0006h
16 bits
RST/
PWR
Core
RO;
RO; RW;
Reserved ():
Fast Back-to-Back Enable (FB2B):
This bit controls whether or not the master
can do fast back-to-back write. Since device
0 is strictly a target this bit is not
implemented and is hardwired to 0. Writes
to this bit position have no effect.
SERR Enable (SERRE):
This bit is a global enable bit for Device 0
SERR messaging. The CPU Uncore does not
have an SERR signal. The CPU Uncore
communicates the SERR condition by
sending an SERR message over DMI to the
SouthBridge.
1: The CPU Uncore is enabled to generate
SERR messages over DMI for specific Device
0 error conditions that are individually
enabled in the ERRCMD and DMIUEMSK
Device Identification Number (DID):
Identifier assigned to the CPU Uncore
core/primary PCI device.
The device IDs for PNV family are:
A00X: Intel® Atom
D500 Series for DT
A01X: Intel® Atom
Series for MB
Description
Description
TM
TM
Processor N400
Processor D400 and
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