AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet - Page 37
AU80610004671AAS LBMH
Manufacturer Part Number
AU80610004671AAS LBMH
Description
MPU, ATOM PROCESSOR, D410, FC-BGA8
Manufacturer
Intel
Series
ATOM - D400r
Datasheet
1.AU80610004392AAS_LBLA.pdf
(153 pages)
Specifications of AU80610004671AAS LBMH
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Operating Temperature Range
0°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Processor Configuration Registers
1.5.10
1.5.11
1.5.12
Datasheet
SID - Subsystem Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
CAPPTR - Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
capability in the capability list.
PXPEPBAR - PCI Express Egress Port Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the PCI Express Egress Port MMIO Configuration space.
There is no physical memory within this 4KB window that can be addressed. The 4KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the EGRESS port MMIO configuration space is disabled and must be
enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0].
This value is used to identify a particular subsystem.
15:0
The CAPPTR provides the offset that is the pointer to the location of the first device
7:0
Bit
Bit
Access
Access
RWO
RO
Default
Default
Value
0000h
Value
E0h
RST/
RST/
PWR
PWR
Core
Core
0/0/0/PCI
2E-2Fh
0000h
16 bits
0/0/0/PCI
34h
E0h
8 bits
0/0/0/PCI
40-47h
0000000000000000h
64 bits
RWO;
RO;
RW/L; RO;
Subsystem ID (SUBID):
This field should be programmed during BIOS
initialization. After it has been written once, it
becomes read only.
Capabilities Pointer (CAPPTR):
Pointer to the offset of the first capability ID
register block. In this case the first capability
is the product-specific Capability Identifier
(CAPID0).
Description
Description
37
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