CH80566EE025DW S LGPN Intel, CH80566EE025DW S LGPN Datasheet - Page 17

• Manufacturer Part Number: CH80566EE025DW S LGPN
• Description: MPU, ATOM PROCESSOR, Z530P, U-FCBGA8
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of CH80566EE025DW S LGPN

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 533MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 437
• Supply Voltage Range: 0.8V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low Power Features
2.1.1.2.2
2.1.1.3
2.1.1.3.1
Datasheet
Stop-Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in Stop-
Grant state by entering the Stop-Grant Snoop state. The processor will stay in this
state until the snoop on the FSB has been serviced (whether by the processor or
another agent on the FSB) or the interrupt has been latched. The processor returns to
the Stop-Grant state once the snoop has been serviced or the interrupt has been
latched.
C4 State
Individual threads of the processor can enter the C4 state by initiating a P_LVL4 I/O
read to the P_BLK or an MWAIT(C4) instruction. Attempts to request C3 will also
covert to C4 requests. If both processor threads are in C4, the central power
management logic will request that the entire processor enter the Deeper Sleep
package low-power state using the sequence through the Sleep and Deep Sleep states
all described in the following sections.
To enable the package level Intel Enhanced Deeper Sleep state, Dynamic Cache Sizing
and Intel Enhanced Deeper Sleep state fields must be configured in the
PMG_CST_CONFIG_CONTROL MSR. Refer to Section 2.1.1.3.3 for further details on
Intel Enhanced Deeper Sleep state.
Sleep State
The Sleep state is a low-power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is
entered through assertion of the SLP# signal while in the Stop-Grant state and is only
a transition state for Intel Atom processor Z5xx series. The SLP# pin should only be
asserted when the processor is in the Stop-Grant state. SLP# assertion while the
processor is not in the Stop-Grant state is out of specification and may result in
unapproved operation.
In the Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP#, DPSLP#, or RESET#) are allowed on the FSB while the processor is in Sleep
state. Snoop events that occur while in Sleep state or during a transition into or out of
Sleep state will cause unpredictable behavior. Any transition on an input signal before
the processor has returned to the Stop-Grant state will result in unpredictable
behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor will reset itself, ignoring
the transition through Stop-Grant state. If RESET# is driven active while the processor
is in the Sleep state, the SLP# and STPCLK# signals should be de-asserted
immediately after RESET# is asserted to ensure the processor correctly executes the
Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state, by asserting the DPSLP# pin (see Section 2.1.1.3.2).
While the processor is in the Sleep state, the SLP# pin must be de-asserted if another
asynchronous FSB event occurs.
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