CH80566EE025DW S LGPN Intel, CH80566EE025DW S LGPN Datasheet - Page 24

• Manufacturer Part Number: CH80566EE025DW S LGPN
• Description: MPU, ATOM PROCESSOR, Z530P, U-FCBGA8
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of CH80566EE025DW S LGPN

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 533MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 437
• Supply Voltage Range: 0.8V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Caution: Enhanced Stop-Grant and Enhanced Deeper Sleep must be enabled using the
Note: Long-term reliability cannot be assured unless all the Enhanced Low-Power States are
Enhanced Low-Power States
Enhanced low-power states (C1E, C2E, and C4E) optimize for power by forcibly
reducing the performance state of the processor when it enters a package low-power
state. Instead of directly transitioning into the package low-power state, the enhanced
package low-power state first reduces the performance state of the processor by
performing an Enhanced Intel SpeedStep Technology transition down to the lowest
operating point. Upon receiving a break event from the package low-power state,
control will be returned to software while an Enhanced Intel SpeedStep Technology
transition up to the initial operating point occurs. The advantage of this feature is that
it significantly reduces leakage while in the Stop-Grant and Deeper Sleep states.
enabled.
The processor implements two software interfaces for requesting enhanced package
low-power states: MWAIT instruction extensions with sub-state hints and using BIOS
by configuring IA32_MISC_ENABLES MSR bits to automatically promote package low-
power states to enhanced package low-power states.
BIOS for the processor to remain within specification. Not complying with this
guideline may affect the long-term reliability of the processor.
Enhanced Intel SpeedStep® Technology transitions are multi-step processes that
require clocked control. These transitions cannot occur when the processor is in the
Sleep or Deep Sleep package low-power states since processor clocks are not active in
these states. Enhanced Deeper Sleep is an exception to this rule when the Hard C4E
configuration is enabled in the IA32_MISC_ENABLES MSR. This Enhanced Deeper
Sleep state configuration will lower core voltage to the Deeper Sleep level while in
Deeper Sleep and, upon exit, will automatically transition to the lowest operating
voltage and frequency to reduce snoop service latency. The transition to the lowest
operating point or back to the original software requested point may not be
instantaneous. Furthermore, upon very frequent transitions between active and idle
states, the transitions may lag behind the idle state entry resulting in the processor
either executing for a longer time at the lowest operating point or running idle at a
high operating point. Observations and analyses show this behavior should not
significantly impact total power savings or performance score while providing power
benefits in most other cases.
Low Power Features
Datasheet