CH80566EE025DW S LGPN Intel, CH80566EE025DW S LGPN Datasheet - Page 61

• Manufacturer Part Number: CH80566EE025DW S LGPN
• Description: MPU, ATOM PROCESSOR, Z530P, U-FCBGA8
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of CH80566EE025DW S LGPN

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 533MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 437
• Supply Voltage Range: 0.8V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Package Mechanical Specifications and Pin Information
Datasheet
PWRGOOD
REQ[4:0]#
RESET#
RS[2:0]#
RSVD
SLP#
SMI#
Signal Name
Reserved
Type
I/O
I
I
I
I
I
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. “Clean”
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies
are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD
can be driven inactive at any time, but clocks and power must
again be stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor—it is
used to protect internal circuits against voltage sequencing
issues. It should be driven high throughout boundary scan
operation.
REQ[4:0]# (Request Command) must connect the appropriate
pins of both FSB agents. They are asserted by the current bus
owner to define the currently active transaction type. These
signals are source synchronous to ADSTB[0]#.
Asserting the RESET# signal resets the processor to a known
state and invalidates its internal caches without writing back any
of their contents. For a power-on Reset, RESET# must stay
active for at least two milliseconds after V
reached their proper specifications. On observing active RESET#,
both FSB agents will de-assert their outputs within two clocks. All
processor straps must be valid within the specified setup time
before RESET# is de-asserted.
RS[2:0]# (Response Status) are driven by the response agent
(the agent responsible for completion of the current transaction),
and must connect the appropriate pins of both FSB agents.
RSVD[3:0] pins E10, E8, D7 and D9 must be tied directly to V
to ensure proper operation of the processor. All other RSVD
signals can be left as No Connects.
SLP# (Sleep), when asserted in Stop-Grant state, causes the
processor to enter the Sleep state. During Sleep state, the
processor stops providing internal clock signals to all units,
leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts.
The processor will recognize only assertion of the RESET# signal,
de-assertion of SLP#, and removal of the BCLK input while in
Sleep state. If SLP# is de-asserted, the processor exits Sleep
state and returns to Stop-Grant state, restarting its internal clock
signals to the bus and processor core units. If DPSLP# is
asserted while in the Sleep state, the processor will exit the
Sleep state and transition to the Deep Sleep state.
SMI# (System Management Interrupt) is asserted
asynchronously by system logic. On accepting a System
Management Interrupt, the processor saves the current state and
enters System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program
execution from the SMM handler. If SMI# is asserted during the
de-assertion of RESET# the processor will tri-state its outputs.
Description
CC
and BCLK have
CCP
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