P89LPC9103FTK NXP Semiconductors, P89LPC9103FTK Datasheet - Page 27

• Manufacturer Part Number: P89LPC9103FTK
• Description: MCU 8BIT 80C51 1K FLASH, HVSON-10
• Manufacturer: NXP Semiconductors

Specifications of P89LPC9103FTK

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 8
• Program Memory Size: 1KB
• Ram Memory Size: 128Byte
• Cpu Speed: 18MHz
• Oscillator Type: Internal Only
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant

NXP Semiconductors
P89LPC9102_9103_9107_3
Product data sheet
8.3.1 Clock definitions
8.3.2 CPU clock (CCLK)
8.2 Enhanced CPU
8.3 Clocks
8.4 On-chip RC oscillator option
The P89LPC9102/9103/9107 uses an enhanced 80C51 CPU which runs at six times the
speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and
most instructions execute in one or two machine cycles.
The P89LPC9102/9103/9107 device has internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of the clock
sources (see
be optionally divided to a slower frequency (see
register”).
Note: f
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executed in one to two machine cycles (two or four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when
enabled, provides an output frequency of 14.746 MHz.
PCLK — Clock for the various peripheral devices and is
The P89LPC9102/9103/9107 provides user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the flash memory is programmed and
include an on-chip watchdog oscillator, an on-chip RC oscillator, and an external clock
input.
The P89LPC9102/9103/9107 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz
temperature. End-user applications can write to the Trim register to adjust the on-chip RC
oscillator to other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1)
the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit
(AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower.
The RCCLK bit (TRIM.7) can be used to switch between the clock source selected by
UCFG1 and the internal RC oscillator. This allows a low frequency source such as the
WDT or low speed external source to clock the device in order to save power and then
switch to the higher speed internal RC oscillator to perform processing.
osc
is defined as the OSCCLK frequency.
Figure 11 “Block diagram of P89LPC9102 oscillator
Rev. 03 — 10 July 2007
8-bit microcontrollers with two-clock accelerated 80C51 core
P89LPC9102/9103/9107
Section 8.8 “CCLK modification: DIVM
CCLK
2
.
control”) and can also
© NXP B.V. 2007. All rights reserved.
1 % at room
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