P89LPC936FA NXP Semiconductors, P89LPC936FA Datasheet - Page 43

• Manufacturer Part Number: P89LPC936FA
• Description: MCU 8BIT 80C51 16K FLASH, PLCC28
• Manufacturer: NXP Semiconductors

Specifications of P89LPC936FA

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 26
• Program Memory Size: 16KB
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 18MHz
• Oscillator Type: External,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
P89LPC933_934_935_936
Product data sheet
Fig 17. SPI block diagram
SPI STATUS REGISTER
BY 4, 16, 64, 128
CPU clock
DIVIDER
SELECT
SPI CONTROL
8.22 SPI
The P89LPC933/934/935/936 provides another high-speed serial communication
interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous
communication bus with two operation modes: Master mode and Slave mode. Up to
3 Mbit/s can be supported in Master mode or up to 2 Mbit/s in Slave mode. It has a
Transfer Completion Flag and Write Collision Flag Protection.
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
Typical connections are shown in
•
•
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected.
interrupt
request
SPI clock (master)
SPI
MSTR
SPEN
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 January 2011
internal
data
bus
8-bit microcontroller with accelerated two-clock 80C51 core
SPI CONTROL REGISTER
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK LOGIC
Figure 18
P89LPC933/934/935/936
clock
through
Figure
20.
M
M
M
S
S
S
CONTROL
LOGIC
PIN
© NXP B.V. 2011. All rights reserved.
002aaa900
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
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