P89V51RB2FN NXP Semiconductors, P89V51RB2FN Datasheet - Page 17

• Manufacturer Part Number: P89V51RB2FN
• Description: IC, MCU 8BIT 80C51 16K FLASH, DIP40
• Manufacturer: NXP Semiconductors

Specifications of P89V51RB2FN

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 32
• Program Memory Size: 16KB
• Ram Memory Size: 1KB
• Cpu Speed: 33MHz
• Oscillator Type: External Only
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
Table 7.
Not bit addressable; Reset value 00H
Table 8.
When instructions access addresses in the upper 128 B (above 7FH), the MCU
determines whether to access the SFRs or RAM by the type of instruction given. If it is
indirect, then RAM is accessed. If it is direct, then an SFR is accessed. See the examples
below.
Indirect Access:
Register R0 points to 90H which is located in the upper address range. Data in ‘#data’ is
written to RAM location 90H rather than port 1.
Direct Access:
Data in ‘#data’ is written to port 1. Instructions that write directly to the address write to the
SFRs.
To access the expanded RAM, the EXTRAM bit must be cleared and MOVX instructions
must be used. The extra 768 B of memory is physically located on the chip and logically
occupies the first 768 B of external memory (addresses 000H to 2FFH).
When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX
instruction in combination with any of the registers R0, R1 of the selected bank or DPTR.
Accessing the expanded RAM does not affect ports P0, P3.6 (WR), P3.7 (RD), or P2.
With EXTRAM = 0, the expanded RAM can be accessed as in the following example.
Expanded RAM Access (Indirect Addressing only):
Bit
7 to 2
1
0
Bit
Symbol
MOV@R0, #data; R0 contains 90H
MOV90H, #data; write data to P1
MOVX@DPTR, A DPTR contains 0A0H
AUXR - Auxiliary register (address 8EH) bit allocation
AUXR - Auxiliary register (address 8EH) bit description
Symbol
-
EXTRAM
AO
7
-
Rev. 05 — 12 November 2009
6
-
Description
Reserved for future use. Should be set to ‘0’ by user programs.
Internal/External RAM access using MOVX @Ri/@DPTR. When ‘0’,
core attempts to access internal XRAM with address specified in
MOVX instruction. If address supplied with this instruction exceeds
on-chip available XRAM, off-chip XRAM is going to be selected and
accessed. When ‘1’, every MOVX @Ri/@DPTR instruction targets
external data memory by default.
ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a
constant rate of
active only during a MOVX or MOVC.
5
-
1
2
the oscillator frequency. In case of AO = 1, ALE is
4
P89V51RB2/RC2/RD2
-
8-bit microcontrollers with 80C51 core
3
-
2
-
EXTRAM
© NXP B.V. 2009. All rights reserved.
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AO
0