CDB4384 Cirrus Logic Inc, CDB4384 Datasheet - Page 35

• Manufacturer Part Number: CDB4384
• Description: Eval Bd 8Chn DAC W/DSD Supt&Low-Latnc DF
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4384

• Number Of Dac's: 8
• Number Of Bits: 24
• Outputs And Type: 8, Single Ended
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS4384
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS4384
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1525

DS620F1
6. REGISTER DESCRIPTION
Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted.
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
PART4
CPEN
7
0
7
0
Chip Revision (Address 01h)
Mode Control 1 (Address 02h)
Part Number ID (PART) [Read Only]
Revision ID (REV) [Read Only]
000 - Revision A0
001 - Revision B0
Function:
This read-only register can be used to identify the model and revision number of the device.
Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user
should write this bit within 10 ms following the release of Reset.
Freeze Controls (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously,
enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
00000- CS4384
FREEZE
PART3
6
0
6
0
DSD/PCM
PART2
5
0
5
0
DAC4_DIS
PART1
4
0
4
0
DAC3_DIS
PART0
3
0
3
0
DAC2_DIS
REV2
2
2
0
-
DAC1_DIS
REV1
1
1
0
-
CS4384
REV0
PDN
0
0
1
-
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