CDB4384 Cirrus Logic Inc, CDB4384 Datasheet - Page 38
![no-image](/images/manufacturer_photos/0/1/141/cirrus_logic_inc_sml.jpg)
CDB4384
Manufacturer Part Number
CDB4384
Description
Eval Bd 8Chn DAC W/DSD Supt&Low-Latnc DF
Manufacturer
Cirrus Logic Inc
Specifications of CDB4384
Number Of Dac's
8
Number Of Bits
24
Outputs And Type
8, Single Ended
Sampling Rate (per Second)
192k
Data Interface
Serial
Dac Type
Voltage
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
CS4384
Description/function
Audio D/A
Operating Supply Voltage
5 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS4384
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
Other names
598-1525
38
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Direct DSD Conversion (DIR_DSD)
Function:
When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control func-
tions.
When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.
In this mode, the full-scale DSD and PCM levels will not be matched (see
performance may be reduced, the volume control is inactive, and the 50 kHz low-pass filter is not available
(see
Static DSD Detect (STATIC_DSD)
Function:
When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE
register.
When set to 0, this function is disabled.
Invalid DSD Detect (INVALID_DSD)
Function:
When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-
tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE
register.
When set to 0 (default), this function is disabled.
DSD Phase Modulation Mode Select (DSD_PM_MODE)
Function:
When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for Phase Modulation
Mode. (See
When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for Phase Modulation Mode.
DSD Phase Modulation Mode Enable (DSD_PM_EN)
Function:
When set to 1, DSD Phase Modulation Input Mode is enabled and the DSD_PM_MODE bit should be set
accordingly.
When set to 0 (default), this function is disabled (DSD normal mode).
Section 2
Figure 20 on page
for filter specifications).
25.)
Section
2), the dynamic range
CS4384
DS620F1