CDB4384 Cirrus Logic Inc, CDB4384 Datasheet - Page 37
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CDB4384
Manufacturer Part Number
CDB4384
Description
Eval Bd 8Chn DAC W/DSD Supt&Low-Latnc DF
Manufacturer
Cirrus Logic Inc
Specifications of CDB4384
Number Of Dac's
8
Number Of Bits
24
Outputs And Type
8, Single Ended
Sampling Rate (per Second)
192k
Data Interface
Serial
Dac Type
Voltage
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
CS4384
Description/function
Audio D/A
Operating Supply Voltage
5 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS4384
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
Other names
598-1525
DS620F1
6.3.2
6.4
6.4.1
DSD_DIF2
DIF3
0
0
0
0
0
0
1
1
1
1
1
X
7
0
DSD Control (Address 04h)
DIF2
Functional Mode (FM)
Default = 11
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Auto Speed Mode detect (32 kHz to 200 kHz sample rates)
Function:
Selects the required range of input sample rates or Auto Speed Mode.
DSD Mode Digital Interface Format (DSD_DIF)
Default = 000 - Format 0 (64x oversampled DSD data with a 4x MCLK to DSD data rate)
Function:
The relationship between the oversampling ratio of the DSD audio data and the required Master clock to
DSD data rate is defined by the Digital Interface Format pins.
The DSD/PCM bit determines whether PCM or DSD Mode is selected.
0
0
0
0
1
1
1
1
DIF2
X
0
0
0
0
1
1
0
0
0
0
1
DSD_DIF1
6
0
DIF1
DIF1
0
0
1
1
0
0
0
0
1
1
0
X
0
0
1
1
0
0
1
1
DSD_DIF0
DIF0
5
0
X
0
1
0
1
0
1
0
1
0
1
0
Table 8. Digital Interface Formats - DSD Mode
Table 7. Digital Interface Formats - PCM Mode
DIFO
0
1
0
1
0
1
0
1
Left Justified, up to 24-bit data
I
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
One-line Mode 1, 24-bit Data +SDIN4
One-line Mode 2, 20-bit Data +SDIN4
One-line Mode 3, 24-bit 6-channel
One-line Mode 4, 20-bit 6-channel
TDM
All other combinations are Reserved
2
S, up to 24-bit data
DIR_DSD
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate.
128x oversampled DSD data with a 3x MCLK to DSD data rate.
128x oversampled DSD data with a 4x MCLK to DSD data rate.
128x oversampled DSD data with a 6x MCLK to DSD data rate.
4
0
STATIC_DSD
DESCRIPTION
3
1
DESCRIPTION
INVALID_DSD
2
1
DSD_PM_MD
1
0
Format
10
11
12
0
1
2
3
4
5
8
9
DSD_PM_EN
CS4384
FIGURE
0
0
10
11
12
13
14
15
16
17
18
19
9
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