CDB4384 Cirrus Logic Inc, CDB4384 Datasheet - Page 36

• Manufacturer Part Number: CDB4384
• Description: Eval Bd 8Chn DAC W/DSD Supt&Low-Latnc DF
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4384

• Number Of Dac's: 8
• Number Of Bits: 24
• Outputs And Type: 8, Single Ended
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS4384
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS4384
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1525

36
6.2.3
6.2.4
6.2.5
6.3
6.3.1
DIF3
7
0
PCM Control (Address 03h)
PCM/DSD Selection (DSD/PCM)
Default = 0
0 - PCM
1 - DSD
Function:
This function selects DSD or PCM Mode. The appropriate data and clocks should be present before
changing modes, or else MUTE should be selected.
DAC Pair Disable (DACx_DIS)
Default = 0
0 - DAC Pair x Enabled
1 - DAC Pair x Disabled
Function:
When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate
the possibility of audible artifacts.
Note:
Format
Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port Mode can occur.
Digital Interface Format (DIF)
Default = 0000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The DSD/PCM bit determines whether
PCM or DSD Mode is selected.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in
Note:
to ensure proper switching from one mode to another.
(DIF)), this function is not available and these bits must be set to 0 for proper operation.
When the device is configured in TDM Mode by setting DIF[3:0] to 1100 (see
While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set
DIF2
6
0
DIF1
5
0
DIF0
4
0
Figures
Reserved
3
0
9-19.
Reserved
2
0
FM1
1
1
Digital Interface
CS4384
DS620F1
FM0
0
1