CS44800-CQZ Cirrus Logic Inc, CS44800-CQZ Datasheet - Page 36

• Manufacturer Part Number: CS44800-CQZ
• Description: IC,Audio Power Amplifier Controller,CMOS,QFP,64PIN
• Manufacturer: Cirrus Logic Inc
• Type: Digital Amplifier Controllerr

Specifications of CS44800-CQZ

• Applications: Automotive Systems
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1532 - BOARD EVAL FOR CS44800 PWM CTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1070

36
4.6
4.6.1
CS
C C L K
C D IN
C D O U T
Control Port Description and Timing
The control port is used to access the registers, allowing the CS44800 to be configured for the desired op-
erational modes and formats. The operation of the control port may be completely asynchronous with re-
spect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required.
The control port has 2 modes: SPI and I²C, with the CS44800 acting as a slave device. SPI mode is selected
if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C mode is
selected by connecting the AD0/CS pin through a resistor to VLC or GND, thereby permanently selecting
the desired AD0 bit address state.
SPI Mode
In SPI mode, CS is the CS44800 chip select signal, CCLK is the control port bit clock (input into the
CS44800 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the
output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling
edge.
Figure 24
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 kΩ resistor, if desired
There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement
after each byte is written, allowing block writes of successive registers. Autoincrement reads are not sup-
ported.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not,
as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.
The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high
impedance state).
ADDRESS
MAP = Memory Address Pointer, 8 bits, MSB first
1001111
C H IP
shows the operation of the control port in SPI mode. To write to a register, bring CS low. The
High Impedance
R/W
M A P
Figure 24. Control Port Timing in SPI Mode
MSB
b y te 1
DATA
b y te n
LSB
A D D R E S S
C H IP
1001111
R/W
MSB
LSB MSB
CS44800
LSB
DS632F1